Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.

Abstract: 3-D ICs (18, 18?, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20).

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ?40, usefully ?10 and preferably ?5.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20?) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30?) of a first aspect ratio containing first conductors (36, 36?) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22?) from the rear surface (22) to form a modified wafer (20?) of smaller final thickness (21?) with a new rear surface (22?), and (iii) forming from the new rear surface (22?), much deeper vias (40, 40?) of second aspect ratios beneath the device region (26) with second conductors (56, 56?) therein contacting the first conductors (36, 36?), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ?40, usefully ?10 and preferably ?5.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18?); etching (104) via cavities (29) partly through the wafer (18?) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18?) with its front side (35) facing a support structure (40); thinning (107) the wafer (18?) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.

Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20?) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30?) of a first aspect ratio containing first conductors (36, 36?) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22?) from the rear surface (22) to form a modified wafer (20?) of smaller final thickness (21?) with a new rear surface (22?), and (iii) forming from the new rear surface (22?), much deeper vias (40, 40?) of second aspect ratios beneath the device region (26) with second conductors (56, 56?) therein contacting the first conductors (36, 36?), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area.

Abstract: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18?); etching (104) via cavities (29) partly through the wafer (18?) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18?) with its front side (35) facing a support structure (40); thinning (107) the wafer (18?) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.

Abstract: 3-D ICs (18, 18?, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20).

Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. First and second substrates (32, 68) are provided. Each substrate has first and second opposing sides. The first substrate (32) has a first microelectronic device formed on the first side (46) thereof, and the second substrate (68) has a second microelectronic device formed on the first side (82) thereof. The first and second substrates (32, 68) are interconnected with at least one support member (100) such that the at least one support member (100) is positioned between the second side (48) of the first substrate (32) and the first side (82) of the second substrate (68). At least one conductive member (98) is provided that electrically connects the first microelectronic device to the second microelectronic device.

Abstract: A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads.

Abstract: A method for forming a microelectronic assembly is provided. A carrier substrate (30) is provided. A sacrificial layer (38) is formed over the carrier substrate. A polymeric layer (40), including a polymeric tape (42) and a polymeric layer adhesive (44), is formed over the sacrificial layer. The polymeric layer adhesive is between the sacrificial layer and the polymeric tape. A microelectronic die (52), having an integrated circuit formed therein, is placed on the polymeric layer. The microelectronic die is encapsulated with an encapsulation material (54) to form an encapsulated structure (58). The polymeric layer and the encapsulated structure are separated from the carrier substrate. The separating of the polymeric layer and the encapsulated structure includes at least partially deteriorating the sacrificial layer.

Abstract: A method and apparatus for improving film stability and moisture resistance of a borophosphosilicate film. The BPSG film according to the present invention is formed under plasma conditions in which high and low frequency RF power is employed to generate the plasma. The high frequency power supply provides most of the energy to break the molecules in the process gas thereby forming the plasma and promoting the necessary reactions. The low frequency power supply regulates and controls ion bombardment of the BPSG film as it is formed. In a preferred embodiment, nitrogen is included in the process gas and the low frequency RF power supply is used to precisely control ion bombardment during deposition processing thereby allowing incorporation of an unexpectedly elevated amount of nitrogen into the film further improving film stability.