Patents by Inventor Chandrasekaran N. Gupta

Chandrasekaran N. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7761729
    Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide-a count signal associated with external device latency. The count signal is captured responsive to the clock signal.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: July 20, 2010
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekaran N. Gupta, Dean C. Moss
  • Patent number: 7280628
    Abstract: Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: October 9, 2007
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekaran N. Gupta, Maria George, Lakshmi Gopalakrishnan
  • Patent number: 7246252
    Abstract: Delay compensation is described. A clock signal used to generate a transmit clock is obtained. Clock cycles are counted to provide a count signal associated with external device latency. The count signal is captured responsive to the clock signal.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: July 17, 2007
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekaran N. Gupta, Dean C. Moss
  • Patent number: 7038466
    Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: May 2, 2006
    Assignee: Xilinx, Inc.
    Inventor: Chandrasekaran N. Gupta
  • Patent number: 6876186
    Abstract: Method and apparatus for determining delay of a circuit. A clock signal is provided to a variable delay and then to the circuit. The clock signal obtained from the circuit is provided to a data register, such as a flip-flop, as a clock input. The clock signal is provided to the flip-flop as a data input. Output of the data register is provided to a controller to incrementally adjust phase shift until the data input and clock input are substantially aligned in phase. All incremental adjustments in phase shift are counted to provide an indication of delay of the circuit.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 5, 2005
    Assignee: XILINX, Inc.
    Inventor: Chandrasekaran N. Gupta