Patents by Inventor ChandraSekhar Desu

ChandraSekhar Desu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Yield profile manipulator
    Patent number: 7930655
    Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: April 19, 2011
    Assignee: LSI Corporation
    Inventors: ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant
  • Yield Profile Manipulator
    Publication number: 20080216048
    Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
    Type: Application
    Filed: May 8, 2008
    Publication date: September 4, 2008
    Applicant: LSI CORPORATION
    Inventors: ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant
  • Yield profile manipulator
    Patent number: 7395522
    Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: July 1, 2008
    Assignee: LSI Corporation
    Inventors: ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant