Patents by Inventor Chandrasekhar Sriram
Chandrasekhar Sriram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11757479Abstract: A TX-TX pre-compensation system that estimates unwanted coupling in a victim transmit chain caused by an aggressor transmit chain and injects a pre-compensation signal to cancel out the estimated coupling. In some embodiments, a signal measurement module estimates the amplitude, phase, and envelope delay of the coupling and an isolation pre-compensation module generates the pre-compensation signal based on the estimated amplitude, the estimated phase, the estimated envelope delay, and the difference between the carrier frequencies of the transmit chains. Since the phase of the coupling may be affected by the carrier frequency of the transmit chains, in some embodiments the phase of the pre-compensation signal is adjusted in response to a change in carrier frequency. Since the amplitude of the coupling may be affected by attenuator gain settings, in some embodiments the amplitude of the pre-compensation signal may be adjusted in response to a change in attenuator gain setting.Type: GrantFiled: September 29, 2021Date of Patent: September 12, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Venkateshwara Reddy Pothapu, Chandrasekhar Sriram, Raju Kharataram Chaudhari, Sai Vaibhav Batchu, Pankaj Gaur
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Publication number: 20220271783Abstract: A TX-TX pre-compensation system that estimates unwanted coupling in a victim transmit chain caused by an aggressor transmit chain and injects a pre-compensation signal to cancel out the estimated coupling. In some embodiments, a signal measurement module estimates the amplitude, phase, and envelope delay of the coupling and an isolation pre-compensation module generates the pre-compensation signal based on the estimated amplitude, the estimated phase, the estimated envelope delay, and the difference between the carrier frequencies of the transmit chains. Since the phase of the coupling may be affected by the carrier frequency of the transmit chains, in some embodiments the phase of the pre-compensation signal is adjusted in response to a change in carrier frequency. Since the amplitude of the coupling may be affected by attenuator gain settings, in some embodiments the amplitude of the pre-compensation signal may be adjusted in response to a change in attenuator gain setting.Type: ApplicationFiled: September 29, 2021Publication date: August 25, 2022Inventors: Sarma Sundareswara GUNTURI, Venkateshwara Reddy POTHAPU, Chandrasekhar SRIRAM, Raju Kharataram CHAUDHARI, Sai Vaibhav BATCHU, Pankaj GAUR
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Patent number: 11336380Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.Type: GrantFiled: June 19, 2020Date of Patent: May 17, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Jawaharlal Tangudu, Sashidharan Venkatraman
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Patent number: 11239854Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.Type: GrantFiled: October 2, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Pankaj Gupta, Sreenath Narayanan Potty, Ajai Paulose, Chandrasekhar Sriram, Mahesh Ravi Varma, Shabbar Abbasi Vejlani, Neeraj Shrivastava, Himanshu Varshney, Divyeshkumar Mahendrabhai Patel, Raju Kharataram Chaudhari
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Patent number: 11063623Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.Type: GrantFiled: November 22, 2019Date of Patent: July 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Jawaharlal Tangudu, Eeshan Miglani, Jagannathan Venkataraman
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Publication number: 20210105021Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.Type: ApplicationFiled: October 2, 2020Publication date: April 8, 2021Inventors: Jawaharlal TANGUDU, Pankaj GUPTA, Sreenath Narayanan POTTY, Ajai PAULOSE, Chandrasekhar SRIRAM, Mahesh Ravi VARMA, Shabbar Abbasi VEJLANI, Neeraj SHRIVASTAVA, Himanshu VARSHNEY, Divyeshkumar Mahendrabhai PATEL, Raju Kharataram CHAUDHARI
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Patent number: 10924320Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.Type: GrantFiled: July 29, 2019Date of Patent: February 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sthanunathan Ramakrishnan, Chandrasekhar Sriram, Raju Kharataram Chaudhari
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Patent number: 10812294Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.Type: GrantFiled: November 15, 2019Date of Patent: October 20, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Sashidharan Venkatraman, Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Sthanunathan Ramakrishnan, Ram Narayan Krishna Nama Mony
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Publication number: 20200322067Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Jawaharlal TANGUDU, Sashidharan VENKATRAMAN
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Patent number: 10778344Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.Type: GrantFiled: October 23, 2019Date of Patent: September 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sarma Sundareswara Gunturi, Chandrasekhar Sriram, Jawaharlal Tangudu, Sashidharan Venkatraman
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Patent number: 10715376Abstract: An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.Type: GrantFiled: June 18, 2019Date of Patent: July 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaiganesh Balakrishnan, Jawaharlal Tangudu, Sthanunathan Ramakrishnan, Chandrasekhar Sriram
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Publication number: 20200169279Abstract: A non-linearity correction module, an optional droop corrector, and a zero-IF receiver with the non-linearity correction module and an optional droop corrector, wherein the non-linearity correction module is configured to generate a non-linearity term scaled to mitigate an inter-modulation component term of a RF signal received by the zero-IF receiver based on a test signal to enhance linearity in the zero-IF receiver and the optional droop corrector is configured to compensate a droop within a signal band of interest, caused by an analog low pass filter filtering a RF signal received by the zero-IF receiver, before a down-converted RF signal is fed into the non-linearity module.Type: ApplicationFiled: November 22, 2019Publication date: May 28, 2020Inventors: Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Jawaharlal TANGUDU, Eeshan MIGLANI, Jagannathan VENKATARAMAN
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Publication number: 20200169434Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.Type: ApplicationFiled: November 15, 2019Publication date: May 28, 2020Inventors: Jawaharlal TANGUDU, Sashidharan VENKATRAMAN, Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Sthanunathan RAMAKRISHNAN, Ram Narayan KRISHNA NAMA MONY
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Publication number: 20200153675Abstract: An IQ estimation module comprising a powerup state IQ estimator configured to generate powerup state IQ estimates based on a powerup calibration of the IQ estimation module, a steady state IQ estimator configured to generate steady state IQ estimates during a steady state operation of the IQ estimation module, and an IQ estimate extender configured to determine differences between the powerup state IQ estimates and steady state IQ estimates at their respective frequency bins and adjust the powerup state IQ estimates to improve the accuracy of IQ estimates.Type: ApplicationFiled: July 29, 2019Publication date: May 14, 2020Inventors: Sthanunathan RAMAKRISHNAN, Chandrasekhar SRIRAM, Raju Kharataram CHAUDHARI
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Publication number: 20200153516Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.Type: ApplicationFiled: October 23, 2019Publication date: May 14, 2020Inventors: Sarma Sundareswara GUNTURI, Chandrasekhar SRIRAM, Jawaharlal TANGUDU, Sashidharan VENKATRAMAN
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Publication number: 20200145277Abstract: An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.Type: ApplicationFiled: June 18, 2019Publication date: May 7, 2020Inventors: Jaiganesh BALAKRISHNAN, Jawaharlal TANGUDU, Sthanunathan RAMAKRISHNAN, Chandrasekhar SRIRAM
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Patent number: 10615813Abstract: Multi-Nyquist differentiator circuits and a radio frequency sampling receiver that applies a multi-Nyquist differentiator circuit. A multi-Nyquist differentiator includes a fixed coefficient filter, a scaling circuit, and a summation circuit. The fixed coefficient filter is configured to filter digital samples generated by an ADC. The scaling circuit is coupled to an output of the fixed coefficient filter, and is configured to scale output of the fixed coefficient filter based on a selected Nyquist band. The summation circuit is coupled to the scaling circuit, and is configured to generate a derivative of the digital samples based on output of the scaling circuit.Type: GrantFiled: April 30, 2019Date of Patent: April 7, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sriram Murali, Jaiganesh Balakrishnan, Chandrasekhar Sriram, Sashidharan Venkatraman, Jagdish Kumar Agrawal
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Patent number: 10581406Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.Type: GrantFiled: June 11, 2018Date of Patent: March 3, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Karthik Khanna S, Chandrasekhar Sriram, Rajendrakumar Joish, Viswanathan Nagarajan
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Patent number: 10250273Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.Type: GrantFiled: October 24, 2017Date of Patent: April 2, 2019Assignee: Texas Instruments IncorporationInventors: Sthanunathan Ramakrishnan, Sashidharan Venkatraman, Chandrasekhar Sriram, Jawaharlal Tangudu
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Publication number: 20190013795Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.Type: ApplicationFiled: June 11, 2018Publication date: January 10, 2019Inventors: Jawaharlal Tangudu, KARTHIK KHANNA S, Chandrasekhar Sriram, Rajendrakumar Joish, Viswanathan Nagarajan