Abstract: Circuits, methods, and apparatus for transmitting, receiving, aligning and re-synchronizing high-speed single-ended signals by aligning a clock signal to one or more received data signals. A receiver amplifier circuit senses and captures low swing single ended signals at the receiver. Alignment is done on a per pin basis where a clock signal is distributed and independently phase shifted and aligned to each incoming data signal. In one example, a preamble containing a training data pattern is transmitted. The receiver steps through a number of dynamic timing alignment codes, each of which selects a different phase-shifted clock signal. The received data is examined for errors and the optimal clock signal is selected. Periodic dynamic readjustments of multiple clock alignment circuits may be made to compensate for temperature and voltage drift and variations.

Abstract: Circuits, methods, and apparatus that provide accurate on-chip termination impedances for high-speed data interface circuits. One embodiment of the present invention provides a series termination impedance for an output driver as well as shunt termination impedances for a receive circuit. These impedances are dynamically adjusted to match a ratio of an external precision resistor. Multiple coarse and fine-grain adjustments are automatically performed by the hardware. Adjustment may occur at power up or at programmable periodic intervals, and one or both of the impedances may be updated each time an interface begins to transmit or receive data. A specific embodiment utilizes a reference resistance that is made up of a parallel combination of resistors connected through MOS transistors. This resistance is adjusted by connecting or disconnecting the parallel resistors until it matches a ratio of an external resistor.

Abstract: Techniques for analyzing circuit designs based on assertions. An assertion is associated with a circuit structure from the circuit design. The assertion specifies a context of the circuit design in which the circuit structure is to be analyzed, an attribute associated with the circuit structure, and a constraint associated with the attribute. The present invention analyzes the circuit design based on assertions and checks to identify one or more instances of the circuit structure in the circuit design which do not satisfy the constraint specified in the assertion. An assertion may also indicate an action to be performed if the circuit structure does not satisfy the constraint specified in the assertion.

Abstract: A computer system includes a central processing unit which further includes an execution unit and two levels of data cache and an error checking and correcting unit. During error-free operation, external cache fill data is supplied directly to the execution unit while a copy of the data is checked by the error checking and correcting unit. In response to detection of an error by the error checking and correcting unit, the use of the fill data by the execution unit is aborted. Furthermore, the data path for fill data is dynamically reconfigured to force remaining pending fill data to pass through the error checking and correcting unit prior to reaching the execution unit or either of the caches. Once all pending fill data has been processed, the data path is reconfigured back to its error-free mode of operation such that fill data is transmitted directly to the execution unit while a copy of the data is checked by the error checking an correcting unit.