Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.

Abstract: A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the trench to remove a first material (38) from the trench. A second material (44) is deposited to plug the opening to seal an air pocket (40) in the trench. The low permittivity region features air pockets with a high volume because the small size of the opening allows the second material to plug the trench without accumulating significantly in the trench.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a dielectric layer (24) to provide electrical isolation. The semiconductor device (10) includes a drain extension region (101) that extend from a drain region (44) to a gate structure (20). The semiconductor device (10) also has a conductive structure (105) that is adjacent to the gate structure (20).

Abstract: An insulated gate field effect transistor (10) having a reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11) and a drain extension region (25) is formed in the dopant well (13). An oxide layer (26) is formed on the dopant well (13) wherein the oxide layer (26) has a thickness of at least 400 angstroms. A gate structure (61) having a gate shunt portion (32) over a thinned portion of the oxide (26) and a gate extension portion (58) over an unthinned portion of the oxide (26). The thinned portion of the oxide (26) forms a gate oxide of the field effect transistor (10) and the unthinned portion lowers a capacitance of the gate shunt portion (32) of the field effect transistor (10).