Patents by Inventor Chandrashekar NARLA

Chandrashekar NARLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for calibrating the read latency of a DDR DRAM module
    Patent number: 10725681
    Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 28, 2020
    Assignee: Synopsys, Inc.
    Inventors: Gyan Prakash, Nidhir Kumar, Chandrashekar Narla, Praphul Malige
  • A METHOD FOR CALIBRATING THE READ LATENCY OF A DDR DRAM MODULE
    Publication number: 20180357002
    Abstract: A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 13, 2018
    Inventors: GYAN PRAKASH, NIDHIR KUMAR, CHANDRASHEKAR NARLA
  • Method and apparatus for aligning a clock signal and a data strobe signal in a memory system
    Patent number: 8780655
    Abstract: A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: July 15, 2014
    Assignee: ARM Limited
    Inventors: Nidhir Kumar, Gyan Prakash, Chandrashekar Narla
  • METHOD AND APPARATUS FOR ALIGNING A CLOCK SIGNAL AND A DATA STROBE SIGNAL IN A MEMORY SYSTEM
    Publication number: 20140177359
    Abstract: A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided.
    Type: Application
    Filed: December 24, 2012
    Publication date: June 26, 2014
    Applicant: ARM Limited
    Inventors: Nidhir KUMAR, Gyan PRAKASH, Chandrashekar NARLA