Abstract: A method for aborting a command for PCIe based NVMe SSD includes receiving an abort command in an Admin submission queue to abort a target command present in an I/O submission queue of host or in an I/O queue of the NVMe SSD and updating a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command. The abort command includes a slot of the target command to be aborted. Thereafter, the method includes placing the abort command into an Admin queue of the NVMe SSD and executing the abort command using the slot of the target command to be aborted by updating an I/O completion queue of the host with the target command to be aborted. The method further includes updating a head doorbell of the doorbell registers of the NVMe SSD and updating the abort command in an Admin completion queue of the host.

Abstract: A method for aborting a command in PCIe based NVMe SSD includes receiving an abort command in an Admin submission queue to abort a target command present in an I/O submission queue of host or in an I/O queue of the NVMe SSD and updating a tail doorbell of NVMe doorbell registers of the NVMe SSD after receiving the abort command. The abort command includes a slot of the target command to be aborted. Thereafter, the method includes placing the abort command into an Admin queue of the NVMe SSD and executing the abort command using the slot of the target command to be aborted by updating an I/O completion queue of the host with the target command to be aborted. The method further includes updating a head doorbell of the doorbell registers of the NVMe SSD and updating the abort command in an Admin completion queue of the host.

Abstract: A method includes: receiving, by a storage device from a core in a host, a request to provide exclusive resource to a command of a predefined submission queue of a non-volatile memory (NVM) set in the storage device, wherein the request pertains to operating the NVM set in a deterministic state; generating a virtual NVM set identifier for a virtual NVM set based on a predefined mapping of the predefined submission queue and the NVM set; determining a storage controller associated with the NVM set based on a predefined mapping of the predefined submission queue, the NVM set, and the virtual NVM set identifier; enabling at least one core to operate in a Predictable Latency Mode; and operating the storage controller and the NVM set in the deterministic state by allocating predetermined resources to execute the command and return data with a predictable latency.

Abstract: Operation of a non-volatile memory (NVM) storage module may comprise receiving a plurality of commands as associated with a plurality of priority-based queues from a host-memory. A received command is evaluated in accordance with a priority associated with the queue storing the command and a size of the command. The evaluated command is split into a plurality of sub-commands, each of the sub-commands having a size determined in accordance with the evaluation. A predetermined number of hardware resources are allocated for each of the evaluated command based on at least the size of each of the sub-commands to thereby enable a processing of the evaluated command based on the allocated resources. Quality of service (QoS) for the evaluated-command may thus be augmented.

Abstract: A method includes: receiving, by a storage device from a core in a host, a request to provide exclusive resource to a command of a predefined submission queue of a non-volatile memory (NVM) set in the storage device, wherein the request pertains to operating the NVM set in a deterministic state; generating a virtual NVM set identifier for a virtual NVM set based on a predefined mapping of the predefined submission queue and the NVM set; determining a storage controller associated with the NVM set based on a predefined mapping of the predefined submission queue, the NVM set, and the virtual NVM set identifier; enabling at least one core to operate in a Predictable Latency Mode; and operating the storage controller and the NVM set in the deterministic state by allocating predetermined resources to execute the command and return data with a predictable latency.

Abstract: Operation of a non-volatile memory (NVM) storage module may comprise receiving a plurality of commands as associated with a plurality of priority-based queues from a host-memory. A received command is evaluated in accordance with a priority associated with the queue storing the command and a size of the command. The evaluated command is split into a plurality of sub-commands, each of the sub-commands having a size determined in accordance with the evaluation. A predetermined number of hardware resources are allocated for each of the evaluated command based on at least the size of each of the sub-commands to thereby enable a processing of the evaluated command based on the allocated resources. Quality of service (QoS) for the evaluated-command may thus be augmented.

Abstract: A method for managing Logical Block Address (LBA) range overlap checking in a Non-Volatile Memory express (NVMe) based Solid State Drive (SSD) includes detecting, by an LBA-Overlap Check (LOC) module, an overlap between an LBA range of an incoming command with an LBA range of at least one outstanding command in an SSD controller, determining, by the LOC module, an overlap count value corresponding to the incoming command, where the overlap count value indicates occurrence of an overlap between the LBA range of the incoming command and the LBA range of the at least one outstanding command, and executing, by the SSD controller, the incoming command based on the overlap count value corresponding to the incoming command.

Abstract: A method for managing Logical Block Address (LBA) range overlap checking in a Non-Volatile Memory express (NVMe) based Solid State Drive (SSD) includes detecting, by an LBA-Overlap Check (LOC) module, an overlap between an LBA range of an incoming command with an LBA range of at least one outstanding command in an SSD controller, determining, by the LOC module, an overlap count value corresponding to the incoming command, where the overlap count value indicates occurrence of an overlap between the LBA range of the incoming command and the LBA range of the at least one outstanding command, and executing, by the SSD controller, the incoming command based on the overlap count value corresponding to the incoming command.

Abstract: A method for handling a command ID conflict in an NVMe-based solid-state drive (SSD) device includes fetching, from a host submission queue (HSQ), one or more commands submitted by a host device. The fetched commands are checked to determine if there is a command ID conflict. A command ID (CID) error interrupt is communicated to firmware of the SSD device if the command ID conflict is detected. A command validation is performed for the one or more commands on receiving the CID error interrupts. A command response is communicated with additional special information from the device FW to the host device for a command having a command ID conflict. One or more resources associated with the one or more commands are released based on the command response.

Abstract: A solid-state drive (SSD) for handling an Asynchronous Event Request (AER) command includes a command receiving circuit and a command management circuit. The command receiving circuit is configured to receive at least one command from at least one host. The command management circuit is configured to determine if the received at least one command from the at least one host is an AER command, store the AER command into an AER queue reserved for deferred AER command handling, if the received at least one command is the AER command, and generate a dummy response for the AER command and release resources occupied by the AER command.

Abstract: A method for handling a command ID conflict in an NVMe-based solid-state drive (SSD) device includes fetching, from a host submission queue (HSQ), one or more commands submitted by a host device. The fetched commands are checked to determine if there is a command ID conflict. A command ID (CID) error interrupt is communicated to firmware of the SSD device if the command ID conflict is detected. A command validation is performed for the one or more commands on receiving the CID error interrupts. A command response is communicated with additional special information from the device FW to the host device for a command having a command ID conflict. One or more resources associated with the one or more commands are released based on the command response.

Abstract: A solid-state drive (SSD) for handling an Asynchronous Event Request (AER) command includes a command receiving circuit and a command management circuit. The command receiving circuit is configured to receive at least one command from at least one host. The command management circuit is configured to determine if the received at least one command from the at least one host is an AER command, store the AER command into an AER queue reserved for deferred AER command handling, if the received at least one command is the AER command, and generate a dummy response for the AER command and release resources occupied by the AER command.

Abstract: A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.

Abstract: Memory management in a multi-core solid state drive (SSD) includes distributing, by a memory access management system, multiple direct memory access (DMA) descriptors that describe a mechanism to access a local memory of each processor among multiple processors in the multi-core solid state drive. A direct memory access engine is configured with logical addresses corresponding to locations described by the direct memory access descriptors in the local memory of each processor. The logical addresses emulate a continuous memory.

Abstract: A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.