Patents by Inventor CHANDRASHEKHAR MUTUGUPPE VENKATARAMANA

CHANDRASHEKHAR MUTUGUPPE VENKATARAMANA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10436838
    Abstract: The present disclosure is directed to systems and methods for autonomously generating test methods for testing features included on semiconductor platforms. The systems and methods described herein either manually or autonomously receive information and/or data indicative of the features included in, on, or about a semiconductor platform to be tested. Based on the presence of features and/or feature combinations on the semiconductor platform, the systems and methods described herein autonomously select the appropriate test blocks used to generate the test method. The systems and methods described herein generate additional test methods as permutations of the selected test blocks. The validity of each test method is confirmed using dependency rules and all valid test methods are combined to form a test package that is used to test the semiconductor platform.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Sneha S. Pingle, Soumya P. Mukherjee, Chandrashekhar Mutuguppe Venkataramana, Divya Appaji Lalithamba
  • Publication number: 20180277235
    Abstract: The present disclosure is directed to systems and methods for autonomously generating test methods for testing features included on semiconductor platforms. The systems and methods described herein either manually or autonomously receive information and/or data indicative of the features included in, on, or about a semiconductor platform to be tested. Based on the presence of features and/or feature combinations on the semiconductor platform, the systems and methods described herein autonomously select the appropriate test blocks used to generate the test method. The systems and methods described herein generate additional test methods as permutations of the selected test blocks. The validity of each test method is confirmed using dependency rules and all valid test methods are combined to form a test package that is used to test the semiconductor platform.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 27, 2018
    Applicant: Intel Corporation
    Inventors: SNEHA S. PINGLE, SOUMYA P. MUKHERJEE, CHANDRASHEKHAR MUTUGUPPE VENKATARAMANA, DIVYA APPAJI LALITHAMBA