Abstract: A device for simultaneous data input and output and program execution support in digital processors is disclosed. The device includes a plurality of controllable input and output ports for inputting and outputting data from the device, a data cache memory which is selectively couplable to each of the plurality of input and output ports, and a controller for controlling the plurality of input and output ports and the data cache memory. The connectivity and controlablity provided by the present invention effectuates a transfer of data between any of the plurality of input and output ports or the data cache memory. The device provides multiport high-speed and high-throughput non-multiplexed data input and output while maintaining the speed and throughput characteristics of the digital processor because the input/output data transfer takes place simultaneously with digital processor program execution. The processor need not wait for data transfers from external data sources when this device is used.

Abstract: A digital peak and valley detector including a peak value address register, a valley value address register, a peak value data register, a valley value data register, a peak comparator for comparing the value stored in the peak value data register with value data contained in the digital signal applied to the digital peak and valley detector and for causing the greater of the two to be stored in the peak value data register while simultaneously storing the address in the peak value address register and a valley comparator for comparing the valley value contained in the valley value data register with the value data contained in the digital signal applied to the digital peak and valley detector for determining which is less and for causing the value and the address of the smaller of the two to be stored respectively in the valley value data and the valley value address registers.