Abstract: A resolver-to-digital converter, comprising: a feedback (FB) filter chain loop having a state observer configured to estimate a rotation speed and a rotation angle of an object, based on a pair of input sine and cosine signals that are amplitude-modulated (AM) to correspond with the rotation angle of the object; and a feedforward (FF) filter chain path configured to estimate the rotation speed of the object based on the pair of input sine and cosine signals, wherein the state observer of the FB filter chain loop is further configured to offset the estimated rotation speed of the FB filter chain loop with the estimated rotation speed of the FF filter chain path to decrease a settling time of the estimated rotation angle.

Abstract: A resolver-to-digital converter, comprising: a feedback (FB) filter chain loop having a state observer configured to estimate a rotation speed and a rotation angle of an object, based on a pair of input sine and cosine signals that are amplitude-modulated (AM) to correspond with the rotation angle of the object; and a feedforward (FF) filter chain path configured to estimate the rotation speed of the object based on the pair of input sine and cosine signals, wherein the state observer of the FB filter chain loop is further configured to offset the estimated rotation speed of the FB filter chain loop with the estimated rotation speed of the FF filter chain path to decrease a settling time of the estimated rotation angle.

Abstract: An emulation modeling apparatus (54) comprises a combination of a device under simulation (48) to be emulated and means for keeping the device under simulation (48) in a quiescent state at normal operating speeds and in a normal operating sequence so as to allow dual access to the emulation modeling apparatus (54) without loss of data or accuracy of functions. One access is from a host simulation environment (26) while the other is from a model debug user interface (20) where internal architecturally visible registers and status are available to the user for greater debug control on the simulated subsystem within simulation environment (26). Specifically, any of a wide variety of physical VLSI circuits (48) to be modeled is kept in a quiescent state after power-on by a device control (50). It is then accessed through simulation means by simulated subsystem within a simulation environment (26), to change the architecturally visible internal state of the VLSI circuit (48).