Patents by Inventor Chang A. Yang

Chang A. Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146554
    Abstract: A method for tokenizing assets via a blockchain-to-blockchain bridge may include: receiving a first instruction from a client to mint first tokens for a client asset; encumbering the client asset on a custody ledger; creating a balance of the first tokens on a first distributed ledger; receiving a second instruction to lock and mint the first tokens to a second distributed ledger as second tokens; receiving verification from a custodian that the first tokens are locked on a lock ledger for the custodian; instructing a blockchain bridge computer program to mint second tokens to a client address on the second distributed ledger; receiving a third instruction to return the second tokens to the first distributed ledger; executing a public burn of the second tokens on the second distributed ledger; and instructing the custodian to unlock the first tokens and move the first tokens to the first distributed ledger.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 2, 2024
    Inventors: Suresh SHETTY, Sudhir UPADHYAY, Manmeet AHLUWALIA, Anthony KLAUSING, Ganesh ANANTWAR, Sophia WASSERMAN, Keerthi MOUDGAL, Chang Yang JIAO, Aditya Mayur TADAY, Tyrone D. LOBBAN, Nikhil SHARMA
  • Publication number: 20240145596
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
  • Patent number: 11969844
    Abstract: A method for detecting and compensating CNC tools being implemented in an electronic device, receives from a detector first parameters and second parameters in respect of a first tool. Such first parameters include at least one of service life, blade break information, and blade chipping information of the first tool, and such second parameters include at least one of length extension information, length wear information, radial wear information, and blade thickness wear information of the first tool. Based on the first parameters, instructions to process the workpiece are transmitted or not. Upon receiving the second parameters, instructions to adjust operation of the first tool are transmitted, to compensate for deterioration in normal use.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 30, 2024
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventors: Hsing-Chih Hsu, Zhao-Yao Yi, Lei Zhu, Chang-Li Zhang, Er-Yang Ma, Chih-Sheng Lin, Feng Xie, Ming-Tao Luo
  • Patent number: 11972072
    Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: April 30, 2024
    Assignee: InnoLux Corporation
    Inventors: Shu-Fen Li, Chuan-Chi Chien, Hsiao-Feng Liao, Rui-An Yu, Chang-Chiang Cheng, Po-Yang Chen, I-An Yao
  • Publication number: 20240134114
    Abstract: A dispersion-compensation microstructure fiber uses pure silica glass as the background material. It includes the core, the first-type defects, the second-type defects and the cladding. The air holes in the fiber cross section are arranged in the equilateral triangle lattice with the same adjacent air-hole to air-hole spacing. The core is formed by omitting 1 air hole. The first-type defects are formed by the 6 air holes locating at the vertices of hexagonal third-layer porous structure surrounding the core and their surrounding background material. The second-type defects are formed by the air holes in the first air-hole layer surrounding each first-type defect and their surrounding background material. The second-type defects act as the porous structure to surround the first-type defects and the fundamental defect modes, and can also combine with the first-type defects to act as the core of the second-order defect modes.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 25, 2024
    Applicant: YANSHAN UNIVERSITY
    Inventors: Wei WANG, Chang ZHAO, Xiaochen KANG, Hongda YANG, Wenchao LI, Zheng LI, Lin SHI
  • Patent number: 11964677
    Abstract: The present invention relates to a platform door control apparatus based on a double 2-vote-2 architecture, including a security communication and logic processing module, a driver collection module, and a maintenance module, the security communication and logic processing module is separately connected to the driver collection module and the maintenance module, and both the security communication and logic processing module and the driver collection module are devices using the double 2-vote-2 architecture. Compared with the prior art, the present invention has the following advantages of effectively improving linkage efficiency of a signal system and a platform door system, and the like.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 23, 2024
    Assignee: CASCO SIGNAL CO., LTD.
    Inventors: Ruiyuan Ye, Xiaolin Tang, Liang Chen, Zhijun Ji, Chang Liu, Chun Yang, Xiaonan Liu, Jing Xu
  • Patent number: 11963970
    Abstract: The present disclosure discloses a preparation method of ginseng composition with high ginsenoside bioavailability. The composition is composed of ginseng powder of 250 meshes or more and ?-cyclodextrin, and the mass ratio of the ginseng powder to the ?-cyclodextrin is 1:0.05. Results show that when ?-cyclodextrin is used as a solid dispersant and added to the 1000-mesh ginseng powder at a mass ratio of 5%, the total dissolution amount is maximum; and furthermore, animal experiments (SD rats) show that the area under the plasma drug concentration-time curve (AUC0-48 h) after 48 h of ginseng powder ingestion is maximum, indicating that in-vivo bioavailability of the ginseng powder is the highest. The method of this application can effectively inhibit the aggregation of the ultra-finely pulverized 1000-mesh ginseng powder by adding the ?-cyclodextrin, thus significantly improving the total dissolution amount of ginsenoside.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: April 23, 2024
    Assignees: JIANGNAN UNIVERSITY, STANDARD FOODS (CHINA) CO., LTD, LE BONTA WELLNESS CO., LTD
    Inventors: Peng Zhou, Changshu Liu, Tao Yang, Chang Liu, Yaowei Liu, Zikuan Zhao, Jianguo Liu, Kexin Li
  • Patent number: 11968156
    Abstract: The present disclosure provides a method for receiving system information in a wireless communication system supporting a TDD narrowband. More specifically, a method performed by a terminal includes receiving first system information from a base station through an anchor carrier, the first system information including operation mode information on an operation mode of the system; determining a location of a non-anchor carrier for receiving second system information based on the operation mode information; and receiving the second system information from the base station through the non-anchor carrier, in which the operation mode information is configured in a guard band or an in-band. In this way, SIB1-NB is also transmitted and received on the non-anchor carrier.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 23, 2024
    Assignee: LG ELECTRONICS INC.
    Inventors: Chang Hwan Park, Seokmin Shin, Seunggye Hwang, Joonkui Ahn, Suckchel Yang
  • Patent number: 11968908
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Publication number: 20240127892
    Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.
    Type: Application
    Filed: April 6, 2023
    Publication date: April 18, 2024
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Yun Cheol KIM, Hae Chang YANG
  • Publication number: 20240128876
    Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
  • Publication number: 20240126127
    Abstract: A cholesteric liquid crystal display device includes a first substrate, a second substrate, a third substrate, a first cholesteric liquid crystal layer, a second cholesteric liquid crystal layer, a first common electrode pattern layer, a second common electrode pattern layer, and a first TFT circuit pattern layer and the second TFT circuit pattern layer. The first cholesteric liquid crystal layer is disposed between the first substrate and the second substrate. The second cholesteric liquid crystal layer is disposed between the second substrate and the third substrate. The first common electrode pattern layer is disposed on the first substrate. The second common electrode pattern layer is disposed on the third substrate. The first TFT circuit pattern layer and the second TFT circuit pattern layer are respectively disposed on two opposite surfaces of the second substrate. The first TFT circuit pattern layer and the second TFT circuit pattern layer are arranged correspondingly.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 18, 2024
    Inventors: CHI-CHANG LIAO, WU-CHANG YANG
  • Publication number: 20240126343
    Abstract: A display device and a panel storage container are provided. The display device includes a display panel including a flat area and a bendable area disposed on a side of the flat area; and a storage container storing the bendable area of the display panel. The bendable area includes an active area having a side adjacent to the flat area, a dummy bending area disposed on another side of the active area, and a dummy flat area disposed on a side of the dummy bending area opposite to the active area. The dummy bending area is interposed between the active area and the dummy flat area, at least a portion of the bendable area is bent with a radius of curvature in the storage container, and a length of the dummy bending area is greater than a length of a portion of which the bendable area is bent.
    Type: Application
    Filed: June 13, 2023
    Publication date: April 18, 2024
    Applicant: Samsung Display Co., LTD.
    Inventors: Tae Chang KIM, Tae Hoon YANG
  • Publication number: 20240130242
    Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Ailian Zhao, Wu-Chang Tsai, Ashim Dutta, Chih-Chao Yang
  • Patent number: 11960201
    Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11962247
    Abstract: A resonant half-bridge flyback power converter includes: a first transistor and a second transistor which form a half-bridge circuit; a transformer and a resonant capacitor connected in series and coupled to the half-bridge circuit; and a switching control circuit configured to generate a first driving signal and a second driving signal to control the first transistor and the second transistor respectively for switching the transformer to generate an output voltage. The first driving signal is configured to magnetize the transformer. The second driving signal includes at most one pulse between two consecutive pulses of the first driving signal. The switching control circuit generates a skipping cycle period when an output power is lower than a predetermined threshold. A resonant pulse of the second driving signal is skipped during the skipping cycle period. The skipping cycle period is increased in response to the decrease of the output power.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: April 16, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Ta-Yung Yang, Ying-Chieh Su, Yu-Chang Chen
  • Patent number: 11963386
    Abstract: A display apparatus includes a base substrate, a light emitting structure disposed on the base substrate, and a thin film encapsulation layer disposed on the light emitting structure and including at least one inorganic layer and at least one organic layer. The at least one inorganic layer includes a high density layer having a density of greater than or equal to about 2.0 g/cm3 and a low density layer having a density of less than about 2.0 g/cm3. The high density layer and the low density layer are in contact with each other.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chang Yeong Song, Won Jong Kim, Yi Su Kim, Jong Woo Kim, Hye In Yang, Woo Suk Jung, Yong Chan Ju, Jae Heung Ha
  • Publication number: 20240120844
    Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 11, 2024
    Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
  • Publication number: 20240120845
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. The second driving signal includes a resonant pulse having a resonant pulse width and a ZVS pulse during the DCM operation. The resonant pulse is configured to demagnetize the transformer. The resonant pulse has a first minimum resonant period for a first level of the output load and a second minimum resonant period for a second level of the output load. The first level is higher than the second level and the second minimum resonant period is shorter than the first minimum resonant period.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Patent number: D1025183
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: April 30, 2024
    Assignee: ViewSonic International Corporation
    Inventors: Jia-Shin Tsai, Shun-Chang Chen, Kun-Tsang Yang