Patents by Inventor Chang-An Hsieh

Chang-An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210164621
    Abstract: A light emitting apparatus includes a housing, a connector, a light source, a control module board, and an antenna. The housing includes an inner space. The light source is located in the inner space. The control module board is located in the connector, wherein an accommodation space is formed by the housing and the control module board. The antenna is located in the accommodation space.
    Type: Application
    Filed: November 27, 2020
    Publication date: June 3, 2021
    Inventors: Sheng-Bo Wang, Chang-Hsieh Wu, Yi-Chao Lin, Yao-Zhong Liu, Jai-Tai Kuo
  • Patent number: 11022946
    Abstract: Reducing nuisance notifications from building automation systems is described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to receive a notification of an alarm from a building automation system, compare attributes of the alarm to attributes of alarms included in a database of suppressed alarms, refrain from transmitting a notification of the alarm to a mobile device in response to the attributes of the alarm matching attributes of any of the alarms in the database, and transmit a notification of the alarm to a mobile device in response to the attributes of the alarm not matching the attributes of any of the alarms in the database.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 1, 2021
    Assignee: Honeywell International Inc.
    Inventors: Gary Fuller, Dae-Soon Kwon, Yi-Chang Hsieh, Andie Kumiawan, Martin Lee, Paul Vanderstraeten
  • Publication number: 20210135898
    Abstract: Devices, methods, and systems for hands free facility status alerts are described herein. One system includes a computing device for hands free building automation notifications, comprising a memory and a processor to execute executable instructions stored in the memory to: receive a notification of an event from a building automation system, modify the notification to include only pre-defined attributes of the notification that are displayable on a user interface of a wearable device, and transmit the modified notification to the wearable device.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 6, 2021
    Inventors: Dae-Soon Kwon, Gary Fuller, Paul Vanderstraeten, Andie Kurniawan, Yi-Chang Hsieh, Martin Lane
  • Patent number: 10996498
    Abstract: A display apparatus with touch sensing and force sensing functions includes a display panel, a first touch device, a conductive layer and a dielectric layer. The first touch device includes multiple touch sensing pads. The conductive layer includes multiple force sensing pads electrically connected to each other, where the touch sensing pads separately overlap the corresponding force sensing pads in a vertical projection direction. The dielectric layer is disposed between the conductive layer and the first touch device. The touch sensing pads, the dielectric layer and the force sensing pads form a force sensing device.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 4, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-San Hsieh, Shih-Lun Lai, Wen-Chang Hsieh, I-Hsiung Huang
  • Publication number: 20210126548
    Abstract: A voltage converter circuit, comprising: a bridge rectifier; a first transistor, having a first end, a second end and a third end; a second transistor, having a first end and a second end; wherein the first end of the first transistor and the first end of second transistor are electrically connected to bridge rectifier, and the second end of the first transistor is electrically connected to the first end of the second transistor; and a Zener diode, connected between the third end of the first transistor and the second end of the second transistor.
    Type: Application
    Filed: July 31, 2020
    Publication date: April 29, 2021
    Inventors: Sheng-Bo Wang, Chiao Fu, Chang-Hsieh Wu, Jai-Tai Kuo, Chao-Kai Chang, Yao-Zhong Liu, Yi-Ru Shen, Chen-Yu Wang
  • Patent number: 10985020
    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chen Lu, Ming-Chang Hsieh, Yi-Min Chen
  • Patent number: 10922021
    Abstract: The disclosure provides a data storage method, a memory storage apparatus, and a memory control circuit unit. The method includes: allocating logical addresses to be mapped to physical programming units of physical erasing units; grouping the logical addresses into logical address groups; receiving write commands and data to be stored into the logical addresses; writing the data into the physical programming units; recording a data write timestamp of each of the physical erasing units; recording a bit sum of each of the logical address groups; and identifying the data belonging to the first logical address group as cold data if the bit sum of a first logical address group is less than a bit sum threshold value and the data write timestamp of the physical erasing units writing data belonging to the first logical address group is less than a timestamp threshold value.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chang Hsieh, Che-Wei Chang
  • Patent number: 10911255
    Abstract: Devices, methods, and systems for hands free facility status alerts are described herein. One system includes a computing device for hands free building automation notifications, comprising a memory and a processor to execute executable instructions stored in the memory to: receive a notification of an event from a building automation system, modify the notification to include only pre-defined attributes of the notification that are displayable on a user interface of a wearable device, and transmit the modified notification to the wearable device.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 2, 2021
    Assignee: Honeywell International Inc.
    Inventors: Dae-Soon Kwon, Gary Fuller, Paul Vanderstraeten, Andie Kurniawan, Yi-Chang Hsieh, Martin Lee
  • Publication number: 20210010499
    Abstract: A locating structure includes a fixture and a locating member. The fixture includes a body and a fastener, wherein the fastener is movably provided at the body. The body is configured to assemble with a first object, and the fastener is configured to fasteningly connect to a second object or be removed from the second object. The locating member is movably assembled with the body, and the locating member may press against or drive the fastener to locate the fastener at a located position, or the locating member may move or drive the fastener to locate the fastener at a locating-released position. Thus, the locating member may be moved to locate the fastener at the located position or at the locating-released position, so as to complete coupling or separation of at least two objects, achieving the effect of repeated quick coupling and separation.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 14, 2021
    Inventors: TING-JUI WANG, WEI-CHEN HUANG, MIN-CHANG HSIEH
  • Publication number: 20200365004
    Abstract: Devices, methods, and systems for translating building automation events into mobile notifications are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to receive a notification of an event from a building automation system, translate the event into a mobile notification of the event, and transmit the mobile notification of the event to a mobile device.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Andie Kurniawan, Gary Fuller, Dae-Soon Kwon, Martin Lee, Paul Vanderstraeten, Yi-Chang Hsieh
  • Publication number: 20200335244
    Abstract: A conductive cable manufacturing method includes the following steps: providing a plurality of first strands and a plurality of second strands, wherein the total quantity of the first strands and the second strands is 2N and N is a positive integer, and the first strands are arranged to form a circle having a gravity center and the gravity center defines a central axis penetrating through the gravity center; twisting the first strands along the central axis in the same direction or interlacing the first strands with each other so as to obtain a central core body; and winding each of the second strands around the central core body clockwise or counterclockwise in order to obtain a conductive cable.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 22, 2020
    Inventor: CHIA-CHANG HSIEH
  • Publication number: 20200293225
    Abstract: The disclosure provides a data storage method, a memory storage apparatus, and a memory control circuit unit. The method includes: allocating logical addresses to be mapped to physical programming units of physical erasing units; grouping the logical addresses into logical address groups; receiving write commands and data to be stored into the logical addresses; writing the data into the physical programming units; recording a data write timestamp of each of the physical erasing units; recording a bit sum of each of the logical address groups; and identifying the data belonging to the first logical address group as cold data if the bit sum of a first logical address group is less than a bit sum threshold value and the data write timestamp of the physical erasing units writing data belonging to the first logical address group is less than a timestamp threshold value.
    Type: Application
    Filed: April 26, 2019
    Publication date: September 17, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yi-Chang Hsieh, Che-Wei Chang
  • Publication number: 20200286782
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
  • Patent number: 10761706
    Abstract: Devices, methods, and systems for navigating an operational user interface for a building management system are described herein. One device includes a user interface, a memory, and a processor configured to execute executable instructions stored in the memory to display, on the user interface of the computing device, an operational user interface for a building management system, wherein the operational user interface includes a number of orthogonal navigation models for the building management system within a single navigation structure, and navigate between the number of orthogonal navigation models within the single navigation structure in the operational user interface.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: September 1, 2020
    Assignee: Honeywell International Inc.
    Inventors: Mark Cockburn, Yi-Chang Hsieh
  • Patent number: 10749290
    Abstract: A waterproof assembly includes a casing, a gasket, and a cap. The casing has an opening. The gasket includes a main body and a protruding portion. The main body has a first circular raised structure configured to abut against an inner surface of the casing. The protruding portion is connected to the main body and is configured to at least partially protrude out of the casing through the opening. The cap is configured to abut against a side of the main body away from the opening. The cap has a through hole configured to be aligned with the protruding portion. The casing further has a plurality of fixing members configured to abut against a side of the cap away from the gasket.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 18, 2020
    Assignee: ACCTON TECHNOLOGY CORPORATION
    Inventor: Chih-Chang Hsieh
  • Publication number: 20200219721
    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 9, 2020
    Inventors: Wen-Chen Lu, Ming-Chang Hsieh, Yi-Min Chen
  • Publication number: 20200211836
    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Wen-Chen Lu, Ming-Chang Hsieh, Yi-Min Chen
  • Patent number: 10672656
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Wen-Hung Tseng
  • Patent number: 10665455
    Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chen Lu, Ming-Chang Hsieh, Yi-Min Chen
  • Publication number: 20200143899
    Abstract: In programming a memory device, a target memory cell is programed by a programming voltage and a programming code. First and second verification voltages are applied on the target memory cell to obtain first and second read data. Whether the target memory cell passes an actual programming verification and/or a pseudo programming verification is determined based on the programming code, the first and the second read data.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Chih-Chang HSIEH, Yung-Chun LI, Ti-Wen CHEN