Patents by Inventor Chang-Bae Lee
Chang-Bae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11658307Abstract: The present disclosure relates to a method and an apparatus for manufacturing a core-shell catalyst, and more particularly, to a method and an apparatus for manufacturing a core-shell catalyst, in which a particle in the form of a core-shell in which the metal nanoparticle is coated with platinum is manufactured by substituting copper and platinum through a method of manufacturing a metal nanoparticle by emitting a laser beam to a metal ingot, and providing a particular electric potential value, and as a result, it is possible to continuously produce nanoscale uniform core-shell catalysts in large quantities.Type: GrantFiled: January 9, 2020Date of Patent: May 23, 2023Assignee: KOREA INSTITUTE OF ENERGY RESEARCHInventors: Gu-Gon Park, Sun-Mi Hwang, Sung-Dae Yim, Chang-Soo Kim, Won-Yong Lee, Tae-Hyun Yang, Seok-Hee Park, Minjin Kim, Young-Jun Sohn, Byungchan Bae, Seung-Gon Kim, Dongwon Shin
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Publication number: 20230057575Abstract: Various embodiments disclose a display driver, wherein the display driver may be configured to detect a defective output buffer among output buffers and perform an output correction function for the defective output buffer.Type: ApplicationFiled: August 18, 2022Publication date: February 23, 2023Applicant: LX Semicon Co., Ltd.Inventors: Byeong Yong KIM, Chang Bae LEE
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Patent number: 11482150Abstract: A display driving device supporting a low power mode according to an aspect of the present disclosure that is capable of minimizing power consumption when driving in the low power mode includes a plurality of output buffers connected to data lines to precharge the data lines with a first data signal corresponding to a black image when a precharge horizontal line is driven in a display panel including a first region where a standby image is displayed and the second region where the black image is displayed, the precharge horizontal line being included in the second region, and a gamma voltage generator connected to the data lines to output the first data signal to the data lines when other horizontal lines other than the precharge horizontal line in the second region are driven.Type: GrantFiled: April 28, 2021Date of Patent: October 25, 2022Assignee: SILICON WORKS CO., LTD.Inventors: Byeong Yong Kim, Chang Bae Lee, Se Jin Choi
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Publication number: 20220024570Abstract: Provided are a flap drive device and a rotorcraft blade, and more particularly, a flap drive device using a two-section link mechanism, which may be applied to a rotorcraft blade, and a rotorcraft blade including the same.Type: ApplicationFiled: May 21, 2021Publication date: January 27, 2022Inventors: Sang Joon SHIN, Won Jong EUN, Byeong Uk IM, Chang Bae LEE, Jin Wook SHIN
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Publication number: 20210350735Abstract: A display driving device supporting a low power mode according to an aspect of the present disclosure that is capable of minimizing power consumption when driving in the low power mode includes a plurality of output buffers connected to data lines to precharge the data lines with a first data signal corresponding to a black image when a precharge horizontal line is driven in a display panel including a first region where a standby image is displayed and the second region where the black image is displayed, the precharge horizontal line being included in the second region, and a gamma voltage generator connected to the data lines to output the first data signal to the data lines when other horizontal lines other than the precharge horizontal line in the second region are driven.Type: ApplicationFiled: April 28, 2021Publication date: November 11, 2021Inventors: Byeong Yong KIM, Chang Bae LEE, Se Jin CHOI
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Publication number: 20210313276Abstract: A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon LEE, Myung Sam KANG, Young Gwan KO, Young Chan KO, Chang Bae LEE
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Patent number: 11062999Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.Type: GrantFiled: September 13, 2019Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon Lee, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
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Patent number: 11002910Abstract: The present invention relates to a fibre optic fusion splicing technique, in particular to a fibre optic fusion splicer for reliable and stable fibre optic fusion splicing, that is characterized by comprising: an alignment part for fixing and aligning first and second optical fibres that are to be fusion spliced; a fusion splicing module having an electrode bar for fusion splicing the first and second optical fibres that are fixed to and aligned in the alignment module; an optical module for photographing the aligned state of the first and second optical fibres aligned by the alignment module, and the fusion-spliced state of the first and second optical fibres fusion-spliced by the fusion splicing module; a support part in which the fusion splicing module and the optical module are mounted; and a lift module for moving the support part up and down.Type: GrantFiled: April 7, 2017Date of Patent: May 11, 2021Assignee: SOLTECH INFONET CO., LTD.Inventors: Chang Hoon Lee, Kyung Jin Youn, Kyeong Ho Sun, Byung Chul Park, Chang Bae Lee, Ji Won Lee
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Patent number: 10852453Abstract: A method for providing an aviation weather chart and an apparatus using the same. An aviation weather chart apparatus according to an aspect of the present invention may compromise: a communication unit which is connected to a weather server and an flight path server so as to acquire aviation weather information from the weather server, acquire flight path information from the flight path server, and acquire flight identification information from a network; and a control unit which acquires the flight path information corresponding to the flight identification information, acquires the aviation weather information corresponding to the flight path information, and acquires an aviation weather chart such that the flight path information and the weather information are displayed at one time on the basis of a flight information region through which a flight corresponding to the flight information passes and the weather information corresponding to the flight information region.Type: GrantFiled: August 18, 2016Date of Patent: December 1, 2020Assignee: IPS INTERNATIONAL PROPERTY LAW FIRMInventors: Wan Sik Won, Chang Bae Lee, Yong Phil Joh
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Publication number: 20200319407Abstract: The present invention relates to a fibre optic fusion splicing technique, in particular to a fibre optic fusion splicer for reliable and stable fibre optic fusion splicing, that is characterized by comprising: an alignment part for fixing and aligning first and second optical fibres that are to be fusion spliced; a fusion splicing module having an electrode bar for fusion splicing the first and second optical fibres that are fixed to and aligned in the alignment module; an optical module for photographing the aligned state of the first and second optical fibres aligned by the alignment module, and the fusion-spliced state of the first and second optical fibres fusion-spliced by the fusion splicing module; a support part in which the fusion splicing module and the optical module are mounted; and a lift module for moving the support part up and down.Type: ApplicationFiled: April 7, 2017Publication date: October 8, 2020Applicant: SOLTECH INFONET CO., LTD.Inventors: Chang Hoon LEE, Kyung Jin YOUN, Kyeong Ho SUN, Byung Chul PARK, Chang Bae LEE, Ji Won LEE
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Patent number: 10727212Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.Type: GrantFiled: October 25, 2018Date of Patent: July 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee Moon, Myung Sam Kang, Young Gwan Ko, Chang Bae Lee, Jin Su Kim
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Publication number: 20200135654Abstract: A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.Type: ApplicationFiled: September 13, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Koon LEE, Myung Sam Kang, Young Gwan Ko, Young Chan Ko, Chang Bae Lee
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Publication number: 20190287953Abstract: A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.Type: ApplicationFiled: October 25, 2018Publication date: September 19, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seon Hee MOON, Myung Sam KANG, Young Gwan KO, Chang Bae LEE, Jin Su KIM
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Patent number: 10312195Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.Type: GrantFiled: November 21, 2017Date of Patent: June 4, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ji Hyun Lee, Jin Gu Kim, Chang Bae Lee, Jin Su Kim
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Patent number: 10229865Abstract: A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least some portions of the first interconnection member and the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the semiconductor chip. The first interconnection member and the second interconnection member respectively include a plurality of redistribution layers electrically connected to the connection pads of the semiconductor chip, and the semiconductor chip has a groove defined in the active surface and between a peripheral edge of the semiconductor chip and the connection pads of the semiconductor chip.Type: GrantFiled: March 28, 2017Date of Patent: March 12, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Jin Seol, Chang Bae Lee, Min Seok Jang
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Patent number: 10186875Abstract: The present invention relates to a coil type unit for wireless power transmission, a wireless power transmission device, an electronic device, and a manufacturing method of a coil type unit for wireless power transmission. A coil type unit for wireless power transmission according to the present invention includes a coil pattern having a wiring pattern shape; a magnetic portion having the coil pattern attached to one surface thereof and a conductive pattern formed thereon; an insulating adhesive portion interposed between the magnetic portion having the conductive pattern formed thereon and the coil pattern to bond the magnetic portion and the coil pattern to each other while insulating the coil pattern and the conductive pattern from each other; and a conductive via for electrically connecting both ends of the coil pattern and the conductive pattern.Type: GrantFiled: August 18, 2014Date of Patent: January 22, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, No Il Park, Doo Sung Jung, Jang Su Kim, Chang Bae Lee
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Publication number: 20190019757Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.Type: ApplicationFiled: November 21, 2017Publication date: January 17, 2019Inventors: Ji Hyun LEE, Jin Gu KIM, Chang Bae LEE, Jin Su KIM
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Publication number: 20180239058Abstract: A method for providing an aviation weather chart and an apparatus using the same. An aviation weather chart apparatus according to an aspect of the present invention may compromise: a communication unit which is connected to a weather server and an flight path server so as to acquire aviation weather information from the weather server, acquire flight path information from the flight path server, and acquire flight identification information from a network; and a control unit which acquires the flight path information corresponding to the flight identification information, acquires the aviation weather information corresponding to the flight path information, and acquires an aviation weather chart such that the flight path information and the weather information are displayed at one time on the basis of a flight information region through which a flight corresponding to the flight information passes and the weather information corresponding to the flight information region.Type: ApplicationFiled: August 18, 2016Publication date: August 23, 2018Applicant: IPS INTERNATIONAL PROPERTY LAW FIRMInventors: Wan Sik WON, Chang Bae LEE, Yong Phil JOH
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Publication number: 20170373029Abstract: A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least some portions of the first interconnection member and the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the semiconductor chip. The first interconnection member and the second interconnection member respectively include a plurality of redistribution layers electrically connected to the connection pads of the semiconductor chip, and the semiconductor chip has a groove defined in the active surface and between a peripheral edge of the semiconductor chip and the connection pads of the semiconductor chip.Type: ApplicationFiled: March 28, 2017Publication date: December 28, 2017Inventors: Yong Jin SEOL, Chang Bae LEE, Min Seok JANG
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Publication number: 20170061189Abstract: Disclosed are sensors for detecting a fingerprint and methods of manufacturing the sensor. The sensor for detecting a fingerprint includes a substrate, first conductor lines formed on a surface of the substrate, an insulating layer formed on the first conductor lines, and second conductor lines formed on the insulating layer. A width of the first conductor lines or a width of the second conductor lines is 1-10 ?m.Type: ApplicationFiled: April 8, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Il KWON, Chang Bae LEE, Hyun Jun KIM, Young Ki LEE