Abstract: An interconnection structure includes a first dielectric layer, a second dielectric layer, first wiring patterns, and a first conductive pattern. The first wiring patterns respectively include a first penetration part that extends into a surface of the first dielectric layer, a first intervention part on the first penetration part and in the second dielectric layer, and a first connection part on the first intervention part and in the second dielectric layer. A top surface of the first intervention part is at a same level as a top surface of the first conductive pattern relative to the surface of the first dielectric layer. An angle between a sidewall of the first connection part and the top surface of the first intervention part is greater than that between a sidewall of the first penetration part and a bottom surface of the first dielectric layer.

Abstract: A semiconductor package includes a first wiring structure including a plurality of first redistribution patterns having a plurality of first bottom connection pads and a plurality of first top connection pads and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns, a second wiring structure including a plurality of second redistribution patterns having a plurality of second bottom connection pads and a plurality of second top connection pads and a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a semiconductor chip interposed between the first wiring structure and the second wiring structure, an encapsulant filling a space between the first wiring structure and the second wiring structure, and a plurality of connection structures passing through the encapsulant and connecting the plurality of first top connection pads to the plurality of second bottom connection pads and arranged arou

Abstract: A semiconductor package includes a first semiconductor package and a second semiconductor package on the first semiconductor package. The first semiconductor package includes a lower redistribution substrate, a connection substrate on the lower redistribution substrate, the connection substrate includes a through hole, a first insulating layer and a through via penetrating the first insulating layer, a lower semiconductor chip in the through hole, a connection layer between the connection substrate and the lower redistribution substrate, the connection layer includes a first metal pattern and a solder pattern on the first metal pattern, a first molding layer on the lower semiconductor chip and the connection substrate, and an upper redistribution substrate on the first molding layer. The second semiconductor package includes a package substrate, an upper semiconductor chip on the package substrate, and a second molding layer on the package substrate and the upper semiconductor chip.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

Abstract: A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.

Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.

Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

Abstract: This invention provides a fan-out semiconductor package ,the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

Abstract: A fan-out type semiconductor package may include a frame, a semiconductor chip, a lower photoimageable dielectric (PID), a lower redistribution layer (RDL), a molding member, a first upper RDL, an upper PID and a second upper RDL. The frame may include an insulation substrate having a cavity and a middle RDL formed through the insulation substrate, with the semiconductor chip arranged in the cavity. The first upper RDL may be arranged on an upper surface of the insulation substrate. The first upper RDL may be connected to an upper end of the middle RDL. The upper PID may be formed on upper surfaces of the frame, the semiconductor chip and the molding member. The second upper RDL may be formed in the upper PID. A photolithography process may be applied to the upper PID so that the second upper RDL formed on the upper PID may have a fine pattern.

Abstract: This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

Abstract: Disclosed are a metal-supported solid oxide fuel cell and a method for manufacturing the metal-supported solid oxide fuel cell. The method includes: fixedly joining a metal support to one surface of a unit cell including a fuel electrode, an air electrode and an electrolyte layer interposed between the fuel and air electrodes to fabricate a metal-supported unit cell (S210); fixing a first separator to the surface of the metal support opposite to the surface thereof to which the unit cell is joined (S220); and assembling the first separator to which the metal-supported unit cell is fixed, an insulating member, a first current collecting member and a second separator (S230). In the metal-supported solid oxide fuel cell, the metal support having a hollow portion in place of a mesh type current collector can be securely sealed to the first separator by direct welding to allow the fuel gas and air to be supplied to the unit cell through respective defined flow passages without being mixed or leakage.

Abstract: The present invention relates to a fabrication method of a solid oxide fuel cell. The fabrication method of a fuel electrode and electrolyte of a solid oxide fuel cell (SOFC) in which a sheet cell including a fuel electrode sheet and an electrolyte sheet is positioned at an upper side of a surface of a fuel electrode pellet, comprising steps of (a) molding and heat-treating powder, in which a fuel electrode material is mixed with a pore forming agent, so as to prepare a fuel electrode pellet; (b) stacking the fuel electrode sheet containing the fuel electrode material and the electrolyte sheet containing an electrolyte material so as to prepare the sheet cell; and (c) coating an adhesive slurry containing the fuel electrode material on the sheet cell or the pellet and adhering the fuel electrode sheet of the sheet cell and the pellet and then heat-treating it.

Abstract: Provided is a metal supported solid oxide fuel cell in which a metal supported cell formed at one side or both sides of a unit cell is directly welded to a separation plate so as to achieve sealing therebetween, thereby preventing fuel gas and air from being leaked or mixed before reaction, and the fuel gas and air are supplied through each assigned passage so as to increase energy production efficiency and also remarkably enhance durability and sealing efficiency.

Abstract: Provided is a fabrication method of a metal supported solid oxide fuel cell (SOFC) which comprises a metal supporter, and an anode layer, an electrolyte and a cathode layer stacked in turn on the metal supporter. The fabrication method includes forming the anode layer and the electrolyte on the metal supporter; forming the green cathode layer by coating on the electrolyte a cathode slurry containing a cathode material; and in-situ sintering the green cathode layer by a normal operation of the metal supported SOFC.

Abstract: Disclosed are a metal-supported solid oxide fuel cell and a method for manufacturing the metal-supported solid oxide fuel cell. The method includes: fixedly joining a metal support to one surface of a unit cell including a fuel electrode, an air electrode and an electrolyte layer interposed between the fuel and air electrodes to fabricate a metal-supported unit cell (S210); fixing a first separator to the surface of the metal support opposite to the surface thereof to which the unit cell is joined (S220); and assembling the first separator to which the metal-supported unit cell is fixed, an insulating member, a first current collecting member and a second separator (S230). In the metal-supported solid oxide fuel cell, the metal support having a hollow portion in place of a mesh type current collector can be securely sealed to the first separator by direct welding to allow the fuel gas and air to be supplied to the unit cell through respective defined flow passages without being mixed or leakage.

Abstract: Disclosed are a metal support for a solid oxide fuel cell and the solid oxide fuel cell including the metal support. The metal support is coupled to a separator of the solid oxide fuel cell by welding and supports one surface of a unit cell comprising a fuel electrode, an air electrode, and an electrolyte layer interposed between the fuel and air electrodes, wherein the metal support is in the form of a plate and has a welding portion welded to the separator on the outer circumference thereof and a hollow portion surrounded by the welding portion to allow a fuel gas or air to flow therethrough. The use of the metal support increases the mechanical strength of the solid oxide fuel cell, resulting in improved durability and extended service life of the solid oxide fuel cell. In addition, the metal support ensures a smooth flow of the fuel gas or air, resulting in an increase in the sealing efficiency and energy production efficiency of the solid oxide fuel cell.