Abstract: A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.

Abstract: A pulse processor includes a phase/pulse width sampler, a first calculator, a second calculator, a latching device, and a pulse width modulator. The phase/pulse width sampler generates an input direction signal, an input phase number and an input pulse width number according to a first signal and a second signal of the command pulse group. The first calculator is used for multiplying the input phase number by P/Q, thereby generating a target phase number, wherein P and Q are positive integers. The second calculator is used for multiplying the input pulse width number by Q/P, thereby generating a target pulse width number. The latching device receives the input direction signal and outputs a target direction signal. The pulse width modulator receives the target direction signal, the target phase number and the target pulse width number, and outputs a transferred pulse group.

Abstract: A pulse processor includes a phase/pulse width sampler, a first calculator, a second calculator, a latching device, and a pulse width modulator. The phase/pulse width sampler generates an input direction signal, an input phase number and an input pulse width number according to a first signal and a second signal of the command pulse group. The first calculator is used for multiplying the input phase number by P/Q, thereby generating a target phase number, wherein P and Q are positive integers. The second calculator is used for multiplying the input pulse width number by Q/P, thereby generating a target pulse width number. The latching device receives the input direction signal and outputs a target direction signal. The pulse width modulator receives the target direction signal, the target phase number and the target pulse width number, and outputs a transferred pulse group.

Abstract: A multi-core processor includes M cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and N cores are configured as co-processors, wherein M and N are positive integers, and N is smaller than M.

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract: A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Abstract: An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit.

Abstract: A redundant system comprising at least two hosts is provided. The redundant system randomly selects one active host under normal operating conditions, and sets the other hosts on stand-by. The active host controls the other hosts and peripheral devices connecting thereto through buses.

Abstract: A data accessing method executed by a processing unit, the method comprising the steps of: (a) decoding an instruction; (b) checking whether the instruction has to be repeated M times to read data with successive addresses in a main memory, wherein the number M is stored in a count register of the processing unit; (c) if the step (b) is true, getting a data from a cache, a pre-fetch buffer, or the main memory, and then decreasing M by one; (d) if M is zero, terminating the data accessing method; (e) determining and pre-fetching data by comparing M to the number of unread data stored in the cache and the pre-fetch buffer; and (f) getting the next data from the cache or the pre-fetch buffer, decreasing M by one, and then returning to step (d).

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract: A selectively-switchable bus connecting device is proposed, which is designed for use in conjunction with a chip device for connecting the multiple signal lines of the chip device's internal bus in a user-specified mapping manner to the multiple signal lines of a socket on an external circuit board. This feature allows chip devices of the same type to be usable for mounting on different types of circuit boards having different socket signal line arrangements, with the benefits of flexible arrangements and cost-effective design and manufacture of circuit boards with chip devices.

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract: A data accessing method and a system for use with the same are provided. A processing unit reads a command from a memory unit and decodes the command. Then, the processing unit determines if the command requires pre-fetching of data that are not stored in a cache or a buffer unit; if yes, the processing unit sends a fetching request to the memory unit according to addresses of data to be fetched and pre-fetched. Moreover, the processing unit reads the data to be fetched from the memory unit and stores the data to be pre-fetched in the buffer unit. Thereby, the above method and system can achieve data pre-fetching accurately.

Abstract: A method and a system for accessing memory data are provided. When an interface unit receives a memory accessing request from a processing unit, a non-cacheable memory buffer unit determines if a memory address corresponds to that in the memory accessing request; if yes, retrieving the memory address; if no, forwarding the memory accessing request to an arbitration unit for accessing data in a memory unit. During transmission of data from the memory unit to the interface unit, the non-cacheable memory buffer unit retrieves the data to simultaneously update stored data. The non-cacheable memory buffer unit pre-reads memory address data following the retrieved data to enhance a data reading speed for the processing unit. During writing data into the memory unit, the non-cacheable memory buffer unit updates the stored data by the written data if a memory address of the written data is identical to that of the stored data.