Patents by Inventor Chang-Chi Lee

Chang-Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12347811
    Abstract: An electronic device is provided. The electronic device includes a first die and a second die. The second die is disposed over the first die. A backside surface of the second die faces a backside surface of the first die. An active surface of the second die is configured to receive a first power. The second die is configured to provide the first die with a second power through the backside surface of the second die and the backside surface of the first die.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: July 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Yen Ting, Pao-Nan Lee, Jung Jui Kang, Chang Chi Lee
  • Publication number: 20250105570
    Abstract: A cable connector includes a shielding shell, a rotating head, and a plurality of wires, wherein the rotating head is pivotally connected to the shielding shell. The rotating head has an enclosing body formed by injection molding. The enclosing body is a solid structure and encloses a circuit board and a connector that are electrically connected to each other. The connector is partially exposed outside the enclosing body. The wires pass through the shielding shell, wherein an end of each wire passes through the enclosing body and is connected to the circuit board. In this way, when the rotating head is pivoted, the wires are not easy to be torn off, which ensures a good electrical connection to enhance the reliability and the stability of the data transmission.
    Type: Application
    Filed: January 25, 2024
    Publication date: March 27, 2025
    Applicant: TAIWAN MASTER HILL TECHNOLOGY CO., LTD.
    Inventor: CHANG-CHI LEE
  • Publication number: 20250054877
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
  • Publication number: 20250038084
    Abstract: An electronic device is disclosed. The electronic device includes an electronic component, an input/output (I/O) signal delivery circuit, and a power delivery circuit. The electronic component has a first surface and a second surface opposite to the first surface. The I/O signal delivery circuit is disposed under the first surface of the electronic component. The power delivery circuit is disposed over the second surface of the electronic component and configured to balance a warpage of the electronic device.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chiung-Ying KUO, Chun-Yen TING, Hung-Chun KUO, Jung Jui KANG, Chang Chi LEE
  • Patent number: 12213247
    Abstract: An electronic device is disclosed. The electronic device includes a carrier, a computing element disposed over the carrier, and a first data storage element disposed over the carrier and electrically connected with the computing element through the carrier. The computing element is configured to receive a first power provided from the first data storage element.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: January 28, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jung Jui Kang, Chang Chi Lee
  • Publication number: 20250029970
    Abstract: The present disclosure provides an electronic device, which includes a circuit structure, a processing component, a first storage unit, and a second storage unit. The processing component is disposed over the circuit structure. The first storage unit is supported by the circuit structure, and electrically connected to the processing component. The second storage unit is disposed under the circuit structure and electrically connected to the processing component via the circuit structure.
    Type: Application
    Filed: July 18, 2023
    Publication date: January 23, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Chang Chi LEE, Hung-Chun KUO, Chun-Yen TING
  • Publication number: 20250022848
    Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
  • Patent number: 12176305
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: December 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Nan Lee, Chen-Chao Wang, Chang Chi Lee
  • Patent number: 12156336
    Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: November 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chiung-Ying Kuo, Hung-Chun Kuo, Pao-Nan Lee, Jung Jui Kang, Chang Chi Lee
  • Patent number: 12132006
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: October 29, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Pao-Nan Lee, Chen-Chao Wang, Chang Chi Lee
  • Publication number: 20240345341
    Abstract: A package device is provided. The package device includes a first die and a first through via structure. The first die has a first optical I/O. The first through via structure is over the first die. A first region of the first through via structure is configured to dissipate heat from the first die and a second region of the first through via structure is configured to transmit an optical signal to or from the first optical I/O.
    Type: Application
    Filed: April 14, 2023
    Publication date: October 17, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Shih-Yuan SUN, Chiu-Wen LEE, Chang Chi LEE, Chun-Yen TING, Hung-Chun KUO
  • Publication number: 20240329344
    Abstract: Semiconductor packages and methods for manufacturing the semiconductor packages are provided. The semiconductor package includes a first electronic element disposed over a first substrate; a second electronic element disposed over a second substrate spaced apart from the first substrate; and a first interconnection element connected to the first electronic element and the second electronic element. The first electronic element extends beyond an edge of the first substrate. The second electronic element extends beyond an edge of the second substrate and towards the first electronic element. The first interconnection element is configured to optically transmit a signal between the first electronic element and the second electronic element.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jung Jui KANG, Chiu-Wen LEE, Shih-Yuan SUN, Chang Chi LEE, Hung-Chun KUO, Chun-Yen TING
  • Patent number: 12107074
    Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: October 1, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chi Lee, Jung Jui Kang, Chiu-Wen Lee, Li Chieh Chen
  • Publication number: 20240264368
    Abstract: An optoelectronic device is provided. The optoelectronic device includes a plurality of first waveguides and a plurality of second waveguides. The plurality of first waveguides are configured to receive a first plurality of optical signals. The plurality of second waveguides are configured to transmit a second plurality of optical signals. The plurality of first waveguides extend substantially along a first direction and the plurality of second waveguides extend substantially along a second direction different from and non-parallel with the first direction.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Chun KUO, Jung Jui KANG, Chiu-Wen LEE, Shih-Yuan SUN, Chang Chi LEE, Chun-Yen TING
  • Publication number: 20240189497
    Abstract: A nasal suction device with a modified handle includes: an extraction structure; a suction structure having a suction head with a suction hole; an air extraction structure including a pump with an air inlet, a piston movably installed in the pump, a handle, a first check valve corresponding to the air inlet, and a second check valve installed to the pump or piston; and a connecting tube with two ends connected to the suction hole and the air inlet respectively. The handle includes a rod connected to the piston, and an operating handle formed outside the pump and including a lever and a connecting section. A finger hole is formed and enclosed by the lever and the inner side of the connecting section, and a finger slot is formed by the lever and the outer side of the connecting section.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 13, 2024
    Inventor: Chang-Chi LEE
  • Patent number: 11991827
    Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: May 21, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Yen Ting, Pao-Nan Lee, Hung-Chun Kuo, Jung Jui Kang, Chang Chi Lee
  • Publication number: 20240155758
    Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
    Type: Application
    Filed: November 4, 2022
    Publication date: May 9, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
  • Patent number: 11967559
    Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 23, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chi Lee, Chiu-Wen Lee, Jung Jui Kang
  • Publication number: 20240128193
    Abstract: An electronic module is disclosed. The electronic module includes an electronic component and an interconnection structure disposed over the electronic component. The interconnection structure comprises a first region and a second region different from the first region. The first region is configured to transmit a power from outside of the electronic module to the electronic component. The second region is configured to dissipate heat from the electronic component.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Chang Chi LEE, Jung Jui KANG
  • Publication number: 20240130043
    Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Yen TING, Pao-Nan LEE, Hung-Chun KUO, Jung Jui KANG, Chang Chi LEE