Patents by Inventor Chang-Chi Lee
Chang-Chi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967559Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.Type: GrantFiled: November 24, 2021Date of Patent: April 23, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chi Lee, Chiu-Wen Lee, Jung Jui Kang
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Publication number: 20240128193Abstract: An electronic module is disclosed. The electronic module includes an electronic component and an interconnection structure disposed over the electronic component. The interconnection structure comprises a first region and a second region different from the first region. The first region is configured to transmit a power from outside of the electronic module to the electronic component. The second region is configured to dissipate heat from the electronic component.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chang Chi LEE, Jung Jui KANG
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Publication number: 20240130043Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Yen TING, Pao-Nan LEE, Hung-Chun KUO, Jung Jui KANG, Chang Chi LEE
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Publication number: 20240055365Abstract: An electronic device is disclosed. The electronic device includes a first interconnection structure, and a first electronic component disposed over the first interconnection structure and having an active surface and a lateral surface. The electronic device also includes a power connection disposed between the first interconnection structure and the active surface of the first electronic component, and a first non-power connection extending along the lateral surface of the first electronic component and electrically connected to the first interconnection structure. The electronic device also includes a second non-power connection disposed between the first interconnection structure and the active surface of the first electronic component. The second non-power connection is configured to block an electromagnetic interference (EMI) between the power connection and the first non-power connection.Type: ApplicationFiled: August 11, 2022Publication date: February 15, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Po-I WU, Jung Jui KANG, Chang Chi LEE, Pao-Nan LEE, Ming-Fong JHONG
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Publication number: 20240038679Abstract: The present disclosure provides an electronic device. The electronic device includes a first electronic component, a first conductive element, and a voltage regulator. The voltage regulator is disposed adjacent to the first electronic component. The voltage regulator is configured to regulate a first voltage from the first EMI shielding layer and to provide the first electronic component with a second voltage.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
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Publication number: 20240030125Abstract: An electronic device is disclosed. The electronic device includes a first circuit structure, a first die, a second die, and a third die. The first die is disposed below the first circuit structure. The second die is disposed below the first circuit structure. The third die is disposed above the first circuit structure and electrically connects the first die to the second die. The first die communicates with the second die through the third die.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jung Jui KANG, Chang Chi LEE
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Publication number: 20240030135Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first region and a second region distinct from the first region. The electronic device also includes an electronic component covering the first region and at least partially exposing the second region. The electronic device also includes a first power regulating element in the second region of the carrier and a second power regulating element. The second power regulating element is disposed adjacent to the first power regulating element and electrically connected to the electronic component through the first power regulating element to provide a first power path.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
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Publication number: 20240023239Abstract: An electronic device is disclosed. The electronic device includes a carrier, a computing element disposed over the carrier, and a first data storage element disposed over the carrier and electrically connected with the computing element through the carrier. The computing element is configured to receive a first power provided from the first data storage element.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jung Jui KANG, Chang Chi LEE
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Publication number: 20240008184Abstract: An electronic device is disclosed. The electronic device includes a carrier including a first portion, a second portion over the first portion, and a third portion connecting the first portion and the second portion. The electronic device also includes a first electronic component disposed between the first portion and the second portion. An active surface of the first electronic component faces the second portion. The electronic device also includes a second electronic component disposed over the second portion. The first portion is configured to transmit a first power signal to a backside surface of the first electronic component opposite to the active surface.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chiung-Ying KUO, Hung-Chun KUO, Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
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Publication number: 20230420418Abstract: An electronic device is provided. The electronic device includes a first die and a second die. The second die is disposed over the first die. A backside surface of the second die faces a backside surface of the first die. An active surface of the second die is configured to receive a first power. The second die is configured to provide the first die with a second power through the backside surface of the second die and the backside surface of the first die.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Yen TING, Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
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Publication number: 20230268293Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
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Publication number: 20230253302Abstract: An electronic package is disclosed. The electronic package includes an electronic component and a plurality of power regulating components. The plurality of power regulating components includes a first power regulating component and a second power regulating component. A first power path is established from the first power regulating component to a backside surface of the electronic component. A second power path is established from the second power regulating component to the backside surface of the electronic component.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
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Publication number: 20230215810Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
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Publication number: 20230207524Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: ApplicationFiled: February 28, 2023Publication date: June 29, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
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Patent number: 11594518Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: GrantFiled: June 3, 2021Date of Patent: February 28, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chi Lee, Jung Jui Kang, Chiu-Wen Lee, Li Chieh Chen
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Publication number: 20220392871Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.Type: ApplicationFiled: June 3, 2021Publication date: December 8, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
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Patent number: 11426508Abstract: A snivel suction apparatus includes a suction mechanism and an air extraction mechanism. The air extraction mechanism is connected to the suction mechanism. The air extraction mechanism includes a pump, a piston, a communicating tube, a first check valve and a second check valve. The piston is arranged on the pump. One side of the communicating tube is connected to the pump. The other side of the communicating tube is connected to the suction mechanism. The first check valve is arranged in the pump and at one side of the communicating tube. The second check valve is arranged on the pump.Type: GrantFiled: October 2, 2019Date of Patent: August 30, 2022Assignee: TAI-SHINY TECHNOLOGY CO., LTD.Inventor: Chang-Chi Lee
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Patent number: 11127650Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.Type: GrantFiled: February 24, 2020Date of Patent: September 21, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chiu-Wen Lee, Hung-Jung Tu, Chang Chi Lee, Chin-Li Kao
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Publication number: 20210265273Abstract: A semiconductor device package includes a plurality of semiconductor chips and an interposer structure. The interposer structure has a plurality of tiers for accommodating the plurality of semiconductor chips. The interposer structure includes at least one conductive via connecting to a pad of the plurality of semiconductor chips.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chiu-Wen LEE, Ian HU, Chang Chi LEE
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Publication number: 20210265231Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first die, a second die, and a thermal dissipation element. The first die has a first surface. The second die is disposed on the first surface. The thermal dissipation element is disposed on the first surface. The thermal dissipation element includes a first portion extending in a first direction substantially parallel to the first surface and partially covered by the second die and a second portion extending in a second direction substantially perpendicular to the first surface to be adjacent to an edge of the second die.Type: ApplicationFiled: February 24, 2020Publication date: August 26, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chiu-Wen LEE, Hung-Jung TU, Chang Chi LEE, Chin-Li KAO