Patents by Inventor Chang Chin TSAI
Chang Chin TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250157863Abstract: A power module is provided. The power module includes a substrate, a semiconductor component, a plurality of pins and a package. The substrate has a first metal surface. The semiconductor component is disposed on the first metal surface. The plurality of pins extends from the first metal surface and is configured to be electrically connected to the semiconductor component. The package body is configured to cover the first metal surface and the semiconductor component, and the package body partially encloses each of the pins. There is a gap between each two adjacent pins, and a separating element is disposed in each gap to increase a creepage distance between the two adjacent pins.Type: ApplicationFiled: June 20, 2024Publication date: May 15, 2025Inventors: Jung-Li CHEN, Yu-Hsuan TSAI, Chang-Chin TSAI, Hsin-Chun CHIANG
-
Publication number: 20250149347Abstract: A method for fabricating a semiconductor packaging structure is provided. The fabrication method includes providing a lower mold. The fabrication method includes disposing a plurality of semiconductor components on the lower mold. The fabrication method includes disposing a plurality of first metal structures on the lower mold, wherein the first metal structures are located on both sides of the semiconductor components. The fabrication method includes providing an upper mold to assemble with the lower mold to accommodate the semiconductor components and the first metal structures. The fabrication method includes filling a packaging material between the lower mold and the upper mold. The fabrication method includes removing the upper mold, the lower mold and the first metal structures to form a plurality of through holes in the packaging material located on both sides of the semiconductor components.Type: ApplicationFiled: April 19, 2024Publication date: May 8, 2025Inventors: Hsin-Chun CHIANG, Chang-Chin TSAI, Jung-Li CHEN, Yu-Hsuan TSAI
-
Publication number: 20240429143Abstract: A power module structure is provided. The power module structure includes a substrate, a chip, a first metal structure, a second metal structure and a packaging material. The chip, the first metal structure and the second metal structure are disposed on the substrate. From a cross-sectional view, the width of the first metal structure is greater than the width of the second metal structure. The packaging material covers the substrate and the chip, and the portions of the first metal structure and the second metal structure are exposed from the upper surface of the packaging material.Type: ApplicationFiled: April 23, 2024Publication date: December 26, 2024Inventors: Jung-Li CHEN, Yu-Hsuan TSAI, Chang-Chin TSAI
-
Patent number: 12094995Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.Type: GrantFiled: August 30, 2022Date of Patent: September 17, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chin Tsai, Yu-Che Huang, Hsun-Wei Chan
-
Patent number: 12040422Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.Type: GrantFiled: August 30, 2022Date of Patent: July 16, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chin Tsai, Yu-Che Huang, Hsun-Wei Chan
-
Publication number: 20240170603Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Yi WU, Chang Chin TSAI, Bo-Yu HUANG, Ying-Chung CHEN
-
Patent number: 11888081Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.Type: GrantFiled: April 9, 2021Date of Patent: January 30, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mei-Yi Wu, Chang Chin Tsai, Bo-Yu Huang, Ying-Chung Chen
-
Patent number: 11551963Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.Type: GrantFiled: February 14, 2020Date of Patent: January 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei Ling Ma, Ying-Chung Chen, Hsin-Ying Ho, Cheng-Ling Huang, Chang Chin Tsai
-
Publication number: 20220416111Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.Type: ApplicationFiled: August 30, 2022Publication date: December 29, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chin TSAI, Yu-Che HUANG, Hsun-Wei CHAN
-
Publication number: 20220328713Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.Type: ApplicationFiled: April 9, 2021Publication date: October 13, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Mei-Yi WU, Chang Chin TSAI, Bo-Yu HUANG, Ying-Chung CHEN
-
Patent number: 11430906Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.Type: GrantFiled: July 22, 2019Date of Patent: August 30, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chin Tsai, Yu-Che Huang, Hsun-Wei Chan
-
Patent number: 11410915Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.Type: GrantFiled: November 3, 2020Date of Patent: August 9, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Che Huang, Chang Chin Tsai
-
Publication number: 20220139812Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.Type: ApplicationFiled: November 3, 2020Publication date: May 5, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Che HUANG, Chang Chin TSAI
-
Publication number: 20210257246Abstract: A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.Type: ApplicationFiled: February 14, 2020Publication date: August 19, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei Ling MA, Ying-Chung CHEN, Hsin-Ying HO, Cheng-Ling HUANG, Chang Chin TSAI
-
Patent number: 11081413Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.Type: GrantFiled: February 21, 2019Date of Patent: August 3, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsin Lin Wu, Yu-Hsuan Tsai, Chang Chin Tsai, Lu-Ming Lai, Ching-Han Huang
-
Patent number: 10770624Abstract: A semiconductor package includes a first substrate having a first surface, a second substrate on the first surface of the first substrate, the second substrate having a first surface and a second surface adjacent to the first surface, and the first surface of the second substrate being disposed on the first surface of the first substrate, and a light source on the second surface of the second substrate. A method for manufacturing the semiconductor device package is also provided.Type: GrantFiled: September 14, 2018Date of Patent: September 8, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chin Tsai, Chun-Han Chen, Hsin-Ying Ho
-
Publication number: 20200035851Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.Type: ApplicationFiled: July 22, 2019Publication date: January 30, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chin TSAI, Yu-Che HUANG, Hsun-Wei CHAN
-
Patent number: 10453760Abstract: A lid array panel includes multiple lids, where each lid includes an outer side wall. The lid array panel further includes a bridge section surrounding and attached to the outer side walls of the lids, where the lids are connected to each other by the bridge section, the lid array panel further includes a reinforcement attached to the bridge section. A package structure includes a carrier, a chip disposed on an upper surface of the carrier, a lid, a bridge section, and a reinforcement. The lid includes a top wall and an outer side wall, the top wall and the outer side wall of the lid together define a cavity, and the outer side wall of the lid is attached to the upper surface of the carrier. The bridge section surrounds, and is attached to, the outer side wall of the lid. The reinforcement is attached to the bridge section.Type: GrantFiled: April 8, 2016Date of Patent: October 22, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang Chin Tsai, Hsun-Wei Chan
-
Publication number: 20190267298Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.Type: ApplicationFiled: February 21, 2019Publication date: August 29, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsin Lin WU, Yu-Hsuan TSAI, Chang Chin TSAI, Lu-Ming LAI, Ching-Han HUANG
-
Publication number: 20190115505Abstract: A semiconductor package includes a first substrate having a first surface, a second substrate on the first surface of the first substrate, the second substrate having a first surface and a second surface adjacent to the first surface, and the first surface of the second substrate being disposed on the first surface of the first substrate, and a light source on the second surface of the second substrate. A method for manufacturing the semiconductor device package is also provided.Type: ApplicationFiled: September 14, 2018Publication date: April 18, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang Chin TSAI, Chun-Han CHEN, Hsin-Ying HO