Patents by Inventor Chang-Chun HSIEH

Chang-Chun HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11158586
    Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 26, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chang-Chun Hsieh, Wu-Der Yang, Ching-Feng Chen
  • Publication number: 20210035916
    Abstract: A semiconductor package includes a substrate, a semiconductor die, a dummy die, a conductive layer, at least one first conductive wire, and at least one second conductive wire. The semiconductor die is disposed on the substrate. The dummy die is disposed on the semiconductor die. The conductive layer is disposed on the dummy die. The first conductive wire electrically connects the semiconductor die to a signal source. The second conductive wire electrically connects the conductive layer to a ground reference.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventor: Chang-Chun HSIEH
  • Publication number: 20200211979
    Abstract: The present disclosure relates to a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate including a first surface and a conductive trace extending over the substrate; a die disposed over the first surface of the substrate; a molding disposed over the first surface of the substrate and covering the die; and a metallic layer surrounding the molding and the substrate, wherein the metallic layer is electrically connected to at least a portion of the conductive trace exposed through the substrate.
    Type: Application
    Filed: April 17, 2019
    Publication date: July 2, 2020
    Inventors: Chang-Chun HSIEH, Wu-Der YANG, Ching-Feng CHEN