Patents by Inventor Chang-Chun Lee
Chang-Chun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127987Abstract: An integrated over-current protection device includes a positive temperature coefficient (PTC) component, a first conductive unit, a second conductive unit, a first conductive via, and a second conductive via. The PTC component includes a first PTC body, and has opposing first and second surfaces. The first conductive unit is disposed on the first surface, and includes a first electrode and a first conductive pad electrically insulated from the first electrode. The second conductive unit is disposed on the second surface, and includes a second electrode and a second conductive pad electrically insulated from the second electrode. The first conductive via extends through the first conductive unit and the PTC component to electrically connect the first electrode to the second conductive pad. The second conductive via extends through the second conductive unit and the PTC component to electrically connect the second electrode to the first conductive pad.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Inventors: Jack Jih-Sang CHEN, Chang-Hung JIANG, Ching-Chiang YEH, Ming-Chun LEE
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Publication number: 20240077973Abstract: A sensor device includes: a sensor panel including sensors arranged in a matrix form and sensor lines electrically connected to the sensors one-to-one; and a sensor driver configured to receive sensing signals from the sensors through the sensor lines, wherein the sensor driver is configured to simultaneously receive a first sensing signal from a first sensor using a first reference signal and a second sensing signal from a second sensor using a second reference signal, wherein the first reference signal and the second reference signal have a same waveform, a phase of the second reference signal is different from a phase of the first reference signal, and wherein a phase of the second sensing signal is different from a phase of the first sensing signal.Type: ApplicationFiled: March 24, 2023Publication date: March 7, 2024Inventors: Jin Woo KIM, Ja Seung KU, Chang Bum KIM, Dong Chun LEE
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Publication number: 20230143470Abstract: Disclosed are small molecule inhibitors of influenza HA, and methods of using them to treat or prevent HA-mediated diseases and conditions.Type: ApplicationFiled: March 30, 2021Publication date: May 11, 2023Inventors: Dennis W. WOLAN, Ian A. WILSON, Yao YAO, Seiya KITAMURA, Nicholas C. WU, Rameshwar U. KADAM, Chang-Chun LEE
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Patent number: 10338251Abstract: Methods and apparatuses for directional designature in shot domain are provided. Azimuth and take-off angles are calculated for each record in the seismic data. Directional designature is then applied to the seismic data using a source signature dependent on the azimuth and take-off angles.Type: GrantFiled: March 24, 2015Date of Patent: July 2, 2019Assignee: CGG SERVICES SASInventors: Chang-Chun Lee, Yunfeng Li, Suryadeep Ray, Gordon Poole
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Publication number: 20170184747Abstract: Methods and apparatuses for directional designature in shot domain are provided. Azimuth and take-off angles are calculated for each record in the seismic data. Directional designature is then applied to the seismic data using a source signature dependent on the azimuth and take-off angles.Type: ApplicationFiled: March 24, 2015Publication date: June 29, 2017Inventors: Chang-Chun LEE, Yunfeng LI, Suryadeep RAY, Gordon POOLE
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Publication number: 20150372138Abstract: A gate configuration with stress impact amplification comprises an element activation zone, at least two source/drain electrodes, a first x direction poly configuration, at least two second x direction dummy poly configurations, at least two y direction dummy poly configurations and two gate electrodes. The at least two source/drain electrodes are located on the element activation zone and are paired as top-down sequence. The first x direction poly configuration is located on the element activation zone, divides the element activation zone into two equal zones and separates the at least two source/drain electrodes. The present invention disperses the stress of the contact-etch-stop-layer (CESL) to the y direction dummy poly configurations.Type: ApplicationFiled: September 25, 2014Publication date: December 24, 2015Applicant: CHUNG YUAN CHRISTIAN UNIVERSITYInventors: Chang-Chun LEE, Chia-Ping HSIEH
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Patent number: 9129957Abstract: A method for forming a metal bump is provided. Firstly, a photo-resist layer is formed on an IC chip by using a lithographic process. The photo-resist layer comprises a metal bump reserved groove and a metal bump slit reserved portion with the extent covering a metal pad. The metal bump slit reserved portion is formed on the metal pad and within the metal bump reserved groove. Then, a deposition process is applied to form the metal bump in the metal bump reserved groove and have the metal bump slit reserved portion penetrating the metal bump. Afterward, the photo-resist layer is removed to leave the metal bump with a metal bump slit therein.Type: GrantFiled: August 18, 2014Date of Patent: September 8, 2015Assignee: CHUNG YUAN CHRISTIAN UNIVERSITYInventors: Ching-Yuan Ho, Chang-Chun Lee
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Publication number: 20110034220Abstract: A handset jacket structure mainly comprises: a upper protecting frame, being a -shaped body, the upper end thereof being opened with a window, one side thereof being indented downward with a proper size of groove, and a proper position of another side thereof being opened with at least one slot corresponding to a connecting hole of the handset; and a lower shielding sheet, configured below the upper protecting frame to form an accepting space between them, being resilient, and having breaches respectively corresponding to the groove and the slot of the upper protecting frame. Whereby, the elasticity of the lower shielding sheet and the groove together with the breaches are operated in coordination with one another to allow a handset to be inserted in the accepting space so as to achieve the protection of the handset.Type: ApplicationFiled: August 7, 2009Publication date: February 10, 2011Inventor: Chang-Chun Lee
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Publication number: 20080042269Abstract: A bump structure for bonding two substrates together includes a composite structure. The composite structure is formed over a first substrate. The composite structure includes at least one first polymer layer and at least one first metal-containing layer. The bump structure also includes a second metal-containing layer at least partially covering a top surface of the composite structure and extending from the top surface of the composite structure to a surface of the first substrate, wherein the second metal-containing layer is thinner than the first metal-containing layer.Type: ApplicationFiled: August 16, 2006Publication date: February 21, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pao-Kang Niu, Chien-Jung Wang, Chang-Chun Lee
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Patent number: 7211886Abstract: The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and a passive component is attached to the flexible substrate by adhesion. In the flexible substrate, electric signals of the electronic device are delivered to the pin terminal through at least a conductive wire for transmitting electric signals. In assembly, the pin terminal of the flexible substrate is inserted into the pin hole of the main substrate. Then, the flexible substrate is folded so as to package the electronic device in a three-dimensional multichip stack manner.Type: GrantFiled: May 22, 2006Date of Patent: May 1, 2007Assignee: Industrial Technology Research InstituteInventors: Yung-Yu Hsu, Kuo-Ning Chiang, Chang-An Yuan, Chang-Chun Lee, Hsien-Chie Cheng
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Publication number: 20060273439Abstract: The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and a passive component is attached to the flexible substrate by adhesion. In the flexible substrate, electric signals of the electronic device are delivered to the pin terminal through at least a conductive wire for transmitting electric signals. In assembly, the pin terminal of the flexible substrate is inserted into the pin hole of the main substrate. Then, the flexible substrate is folded so as to package the electronic device in a three-dimensional multichip stack manner.Type: ApplicationFiled: May 22, 2006Publication date: December 7, 2006Applicant: Industrial Technology Research InstituteInventors: Yung-Yu Hsu, Kuo-Ning Chiang, Chang-An Yuan, Chang-Chun Lee, Hsien-Chie Cheng
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Publication number: 20050224947Abstract: The present invention relates to a three-dimensional multichip stack electronic package structure and method for making the same, including a main substrate having at least a pin-hole set and at least a flexible substrate having at least a pin terminal. At least an electronic device including an active component and a passive component is attached to the flexible substrate by adhesion. In the flexible substrate, electric signals of the electronic device are delivered to the pin terminal through at least a conductive wire for transmitting electric signals. In assembly, the pin terminal of the flexible substrate is inserted into the pin hole of the main substrate. Then, the flexible substrate is folded so as to package the electronic device in a three-dimensional multichip stack manner.Type: ApplicationFiled: October 5, 2004Publication date: October 13, 2005Applicant: Industrial Technology Research InstituteInventors: Yung-Yu Hsu, Kuo-Ning Chiang, Chang-An Yuan, Chang-Chun Lee, Hsien-Chie Cheng