Patents by Inventor Chang-Chun Lin

Chang-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240184671
    Abstract: A using method of a statistics table in a solid state storage device is provided. When the solid state storage device is powered on, the statistics table is loaded from a non-volatile memory into a volatile memory. A content of the statistics table contains plural ranges. The plural ranges respectively correspond to plural counting values. If an update cycle is reached, the statistics table is updated according to a sensed value. A first sum value is calculated according to the plural counting values corresponding to the plural ranges in the statistics table. The timing of enabling a data verification process for the non-volatile memory is determined according to the first sum value and a first threshold value.
    Type: Application
    Filed: May 9, 2023
    Publication date: June 6, 2024
    Inventors: Liang-You LIN, Ya-Ping PAN, Po-Lin LIU, Chang-Chun ZHENG
  • Patent number: 11942169
    Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Kian-Long Lim, Wen-Chun Keng, Chang-Ta Yang, Shih-Hao Lin
  • Patent number: 4776884
    Abstract: A process for determining the arrangement of the layered charges in a blast furnace prior to smelting. Positioned in the layered charges in the blast furnace are a plurality of upright tubes in each of which an eddy current probe is moved up and down. The layered charges are composed of alternate layers of coke and sintered iron ore. A first set of data indicating the position of the probe is obtained through an encoder, a position counter and a recorder. A second set of data indicating the content of the sintered iron ores in the charges at any level is obtained through an eddy current tester and the recorder due to the fact the sintered iron ores and the cokes are of different magnetic permeabilities. By contrasting the first set of data with the second set of data, the distribution of the sintered iron ores in the charges is detected.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: October 11, 1988
    Assignee: China Steel Corporation
    Inventors: Chung-Mei Chen, Jenn-Fu Yang, Chang-Chun Lin, Seng-Her Hong