Abstract: Disclosed herein an apparatus and a method for detecting buried features using backscattered particles. In an example, the apparatus comprises a source of charged particles; a stage; optics configured to direct a beam of the charged particles to a sample supported on the stage; a signal detector configured to detect backscattered particles of the charged particles in the beam from the sample; wherein the signal detector has angular resolution. In an example, the methods comprises obtaining an image of backscattered particles from a region of a sample; determining existence or location of a buried feature based on the image.

Abstract: Disclosed herein an apparatus and a method for detecting buried features using backscattered particles. In an example, the apparatus comprises a source of charged particles; a stage; optics configured to direct a beam of the charged particles to a sample supported on the stage; a signal detector configured to detect backscattered particles of the charged particles in the beam from the sample; wherein the signal detector has angular resolution. In an example, the methods comprises obtaining an image of backscattered particles from a region of a sample; determining existence or location of a buried feature based on the image.

Abstract: A structure, for defect inspection, is provided, which includes a scanning pad scanned by an electron beam inspection tool and a test key. The structure can be located in the scribe line. A virtual grounding pad is further provided if the test key is located in the dummy pattern regions.

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: A method, apparatus and computer readable medium for charged particle beam inspection of a sample comprising at least one sampling region and at least one skip region is disclosed. The method, apparatus and computer readable medium comprise receiving an imaging recipe which at least comprises information of the area of the sampling and skip regions; calculating a default stage speed according to the imaging recipe; calculating an alternative stage speed at least according to the default stage speed, the sampling region area information, and the skip region area information; calculating at least one imaging scan compensation offset at least according to the alternative stage speed; and inspecting the sample at the alternative stage speed while adjusting the motion of the charged particle beam according to the imaging scan compensation offsets, such that the charged particle beam tightly follows the motion of the stage and images only the sampling regions on the sample.

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: A method, apparatus and computer readable medium for charged particle beam inspection of a sample comprising at least one sampling region and at least one skip region is disclosed. The method, apparatus and computer readable medium comprise receiving an imaging recipe which at least comprises information of the area of the sampling and skip regions; calculating a default stage speed according to the imaging recipe; calculating an alternative stage speed at least according to the default stage speed, the sampling region area information, and the skip region area information; calculating at least one imaging scan compensation offset at least according to the alternative stage speed; and inspecting the sample at the alternative stage speed while adjusting the motion of the charged particle beam according to the imaging scan compensation offsets, such that the charged particle beam tightly follows the motion of the stage and images only the sampling regions on the sample.

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: A method, apparatus and computer readable medium for charged particle beam inspection of a sample comprising at least one sampling region and at least one skip region is disclosed. The method, apparatus and computer readable medium comprise receiving an imaging recipe which at least comprises information of the area of the sampling and skip regions; calculating a default stage speed according to the imaging recipe; calculating an alternative stage speed at least according to the default stage speed, the sampling region area information, and the skip region area information; calculating at least one imaging scan compensation offset at least according to the alternative stage speed; and inspecting the sample at the alternative stage speed while adjusting the motion of the charged particle beam according to the imaging scan compensation offsets, such that the charged particle beam tightly follows the motion of the stage and images only the sampling regions on the sample.

Abstract: A method, apparatus and computer readable medium for charged particle beam inspection of a sample comprising at least one sampling region and at least one skip region is disclosed. The method, apparatus and computer readable medium comprise receiving an imaging recipe which at least comprises information of the area of the sampling and skip regions; calculating a default stage speed according to the imaging recipe; calculating an alternative stage speed at least according to the default stage speed, the sampling region area information, and the skip region area information; calculating at least one imaging scan compensation offset at least according to the alternative stage speed; and inspecting the sample at the alternative stage speed while adjusting the motion of the charged particle beam according to the imaging scan compensation offsets, such that the charged particle beam tightly follows the motion of the stage and images only the sampling regions on the sample.

Abstract: A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations.

Abstract: The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Abstract: A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations.

Abstract: A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations.

Abstract: A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations.

Abstract: A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations.