Abstract: The present invention discloses a novel damascene local interconnect process to avoid junction leakage caused by poor interface of the interconnection with isolation edges. The process comprises the steps of: (a) forming a first dielectric layer over the substrate surface; (b) forming an interconnection in the upper level of the dielectric layer which spans over the first and second active areas; (c) forming a second dielectric layer over the first dielectric layer and the interconnection; (d) etching first and second contact holes adjacent to the opposite ends of the interconnection through the second and first dielectric layers, the first and second contact holes extending down to the first and second active area respectively; and (e) filling the first and second contact holes with first and second conductive plugs respectively, wherein the interconnection thereby connects the first and second conductive plugs to couple the first and second active areas.

Abstract: A method of forming ESD protective transistor is disclosed, which is performed by ion implant into the drain contact hole of the ESD protective transistor, wherein the contact hole are fabricated simultaneously with the gate contact holes of the functional transistor and of the ESD protective transistor. Both of the transistors have a respective metal silicide layer cap the polysilicon layer to prevent depleted region formed in the poly-gate for ion implant using p type ions. The p type ions are to increase the instant current tolerance. Alternatively, the ion implant is using n type ions to increase the punchthrough ability of the ESD protective transistor. In the latter case, the metal silicide layer in the gate regions of both transistors is optional.