Patents by Inventor Chang Deok Lee
Chang Deok Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446017Abstract: A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.Type: GrantFiled: September 18, 2009Date of Patent: May 21, 2013Assignee: Amkor Technology Korea, Inc.Inventors: Jong Sik Paek, In Bae Park, Chang Deok Lee
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Patent number: 8198738Abstract: A bond pad and a method of making the same for a semiconductor die has a bonding region formed on the bond pad. A test region is formed on the bond pad and is adjacent to the bonding region.Type: GrantFiled: October 16, 2007Date of Patent: June 12, 2012Assignee: Amkor Technology, Inc.Inventors: Chan Ha Hwang, Do Hyun Na, Chang Deok Lee
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Patent number: 8148724Abstract: A liquid crystal display device includes a gate line and a data line on a substrate crossing each other to define a pixel region; a thin film transistor in the pixel region and connected to the gate line and the data line; a pixel electrode in the pixel region and connected to the thin film transistor; and a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including: a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, at least one side of the pad contact hole having an uneven shape in plane; and a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the pad contact hole.Type: GrantFiled: May 26, 2009Date of Patent: April 3, 2012Assignee: LG Display Co., Ltd.Inventors: Chang-Deok Lee, Hyung-Beom Shin, Seok Kim
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Patent number: 8125064Abstract: In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs.Type: GrantFiled: July 28, 2008Date of Patent: February 28, 2012Assignee: Amkor Technology, Inc.Inventors: Chang Deok Lee, Do Hyun Na
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Publication number: 20110068427Abstract: A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.Type: ApplicationFiled: September 18, 2009Publication date: March 24, 2011Applicant: AMKOR TECHONOLOGY KOREA, INC.Inventors: Jong Sik PAEK, In Bae PARK, Chang Deok LEE
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Patent number: 7808084Abstract: Disclosed is a lead frame, a semiconductor device and a fabrication method related to the semiconductor device. Since the lead frame has a land connecting bar, an upper surface of which is half-etched, the land connecting bar is more easily removed by a blade than a conventional land connecting bar in a fabrication process for the semiconductor device. Accordingly, stress applied to the lands when the land connecting bar is removed is reduced, and a flatness of the lands is maintained. Also, first and second lands constituting the lands are alternately formed with the land connecting bar, leads are alternately formed with the second lands, and wire bonding regions of the leads are positioned on a plane higher than the second lands. Accordingly, an interval between the conductive wires can be constantly maintained and the conductive wires have different traces, thus preventing a short between the conductive wires due to wire sweeping in an encapsulation process.Type: GrantFiled: May 6, 2008Date of Patent: October 5, 2010Assignee: Amkor Technology, Inc.Inventors: Chang Deok Lee, Do Hyun Na
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Patent number: 7760317Abstract: A TFT array substrate is fabricated in a reduced number of processes. The TFT array substrate includes gate and data pads with enlarged contact areas to facilitate contact with an inspecting pin of an inspection device. An LCD incorporating the TFT array substrate is inspected by contacting the inspecting pin to the gate and data pads. The TFT array substrate includes first, second, and third conductive pattern groups. The first conductive pattern group includes a gate electrode, a gate line, and a lower gate pad electrode. The second conductive pattern group includes source and drain electrodes, a data line, and a lower data pad electrode. The third conductive pattern group includes a pixel electrode, and upper gate and data pad electrodes. A semiconductor pattern is along and beneath the second conductive pattern group. Gate insulating and protective film patterns are at areas not occupied by the third conductive pattern group.Type: GrantFiled: October 13, 2004Date of Patent: July 20, 2010Assignee: LG Display Co., Ltd.Inventors: Byoung Ho Lim, Soon Sung Yoo, Chang Deok Lee, Seung Hee Nam, Jae Young Oh, Hong Sik Kim, Hee Young Kwack
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Publication number: 20100127263Abstract: A liquid crystal display device includes a gate line and a data line on a substrate crossing each other to define a pixel region; a thin film transistor in the pixel region and connected to the gate line and the data line; a pixel electrode in the pixel region and connected to the thin film transistor; and a gate pad at an end of the gate line and a data pad at an end of the data line, at least one of the gate pad and the data pad including: a pad electrode including at least one pad contact hole therein along with a passivation layer, the passivation layer on the pad electrode, at least one side of the pad contact hole having an uneven shape in plane; and a pad electrode terminal contacting inner side surfaces of the pad electrode surrounding the pad contact hole.Type: ApplicationFiled: May 26, 2009Publication date: May 27, 2010Inventors: Chang-Deok Lee, Hyung-Beom Shin, Seok Kim
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Patent number: 7705954Abstract: An LCD and a fabrication method thereof are provided. The LCD includes a gate pad. The gate pad includes a gate ITO electrode formed on a substrate, a first and a second gate pad bottom electrode formed on a predetermined region of the gate ITO electrode, a gate insulating layer formed on the first and the second gate pad bottom electrode, a passivation layer formed on the gate insulating layer, a gate pad top electrode formed on the passivation layer, and at least one contact hole. The LCD further comprises a liquid crystal panel having a gate line that has a dual structure integrally formed with the first gate pad bottom electrode and the second gate pad bottom electrode.Type: GrantFiled: June 7, 2006Date of Patent: April 27, 2010Assignee: LG. Display Co., Ltd.Inventor: Chang Deok Lee
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Patent number: 7550327Abstract: This invention provides method for fabricating a thin film transistor substrate that is adaptive for forming a good pattern design and also removing a stepped difference using a three-mask process.Type: GrantFiled: December 4, 2006Date of Patent: June 23, 2009Assignee: LG Display Co., Ltd.Inventors: Chang Deok Lee, Hyun Seok Hong
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Patent number: 7359204Abstract: A memory card including a module comprising at least a printed circuit board having an electronic circuit device mounted thereto and at least one I/O pad and at least one test pad disposed thereon. The module is inserted into a complementary cavity formed within a case of the memory card, such case generally defining the outer appearance of the memory card. The module is secured within the cavity of the case through the use of an adhesive. In each embodiment of the present invention, first and second covers are movably attached to a case for selectively covering or exposing the I/O pads and the test features/pads of the module of the memory card.Type: GrantFiled: February 15, 2006Date of Patent: April 15, 2008Assignee: Amkor Technology, Inc.Inventors: Sang Jae Jang, Chul Woo Park, Jong Woon Choi, Jae Dong Kim, Choon Heung Lee, Chang Deok Lee
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Publication number: 20070155068Abstract: This invention provides method for fabricating a thin film transistor substrate that is adaptive for forming a good pattern design and also removing a stepped difference using a three-mask process.Type: ApplicationFiled: December 4, 2006Publication date: July 5, 2007Inventors: Chang Deok Lee, Hyun Seok Hong
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Publication number: 20070153148Abstract: An LCD and a fabrication method thereof are provided. The LCD includes a gate pad. The gate pad includes a gate ITO electrode formed on a substrate, a first and a second gate pad bottom electrode formed on a predetermined region of the gate ITO electrode, a gate insulating layer formed on the first and the second gate pad bottom electrode, a passivation layer formed on the gate insulating layer, a gate pad top electrode formed on the passivation layer, and at least one contact hole. The LCD further comprises a liquid crystal panel having a gate line that has a dual structure integrally formed with the first gate pad bottom electrode and the second gate pad bottom electrode.Type: ApplicationFiled: June 7, 2006Publication date: July 5, 2007Inventor: Chang Deok Lee
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Patent number: 7227236Abstract: Disclosed are an image sensor package and its manufacturing method. As an example, an infrared ray protection glass is positioned directly on an image sensing region of an image sensor die. An electrically conductive wire and so forth located outside the image sensing region are encapsulated. At this time, one surface of the infrared ray protection glass is exposed outwardly. A mount holder to which a barrel with lenses is coupled is adhered on a surface of the encapsulant outside the infrared ray protection glass. The mount holder has a similar width to that of the image sensor die. Accordingly, the overall width of the image sensor package can become reduced, and the electrically conductive wire is protected against oxidization because it is surrounded by the encapsulant.Type: GrantFiled: April 26, 2005Date of Patent: June 5, 2007Assignee: Amkor Technology, Inc.Inventors: Chang Deok Lee, Do Hyun Na