Abstract: A data transmission circuit includes a data output unit (DOU) connected to a positive data transmission line and a negative data transmission line. The DOU generates a recovered data signal based on data signals communicated via the positive and negative data transmission lines. Data signal driving units are respectively connected at different points along the positive and negative data transmission lines, where each data signal driving unit generates and provides a positive data signal and a negative data signal based on a data input signal and a data transmission distance between the data signal driving unit and the data output unit.

Abstract: An image sensor may include a plurality of pixels, a plurality of sub-pixel groups, respective ones of the sub-pixel groups including at least two pixels among the plurality of pixels, and an analog-to-digital converter configured to perform analog-to-digital conversion on pixel signals output from the plurality of sub-pixel groups and configured to output digital pixel signals responsive to the analog-to-digital conversion. The at least two pixels may have different saturation times.

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N?M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Abstract: A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: a line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.

Abstract: A data transmission circuit includes a data output unit (DOU) connected to a positive data transmission line and a negative data transmission line. The DOU generates a recovered data signal based on data signals communicated via the positive and negative data transmission lines.

Abstract: A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: an line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N?M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.