Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.

Abstract: An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: A current supply includes a current mirror arrangement having a feedback circuit. The current supply includes a current mirror input stage connected to a constant current source providing a reference current; a current mirror output stage providing an output current substantially mirroring the reference current; and a feedback circuit feeding back to the current mirror input stage a feedback signal representing perturbations in the output current to cause the output current to more accurately mirror the reference current. In one embodiment, a dummy current mirror output stage substantially mirrors the reference current, and the feedback circuit receives a signal from the dummy current mirror output stage, and in response thereto, supplies the feedback signal to the current mirror input stage to cause the output current to more accurately mirror the reference current.

Abstract: A current supply includes a current mirror arrangement having a feedback circuit. The current supply includes a current mirror input stage connected to a constant current source providing a reference current; a current mirror output stage providing an output current substantially mirroring the reference current; and a feedback circuit feeding back to the current mirror input stage a feedback signal representing perturbations in the output current to cause the output current to more accurately mirror the reference current. In one embodiment, a dummy current mirror output stage substantially mirrors the reference current, and the feedback circuit receives a signal from the dummy current mirror output stage, and in response thereto, supplies the feedback signal to the current mirror input stage to cause the output current to more accurately mirror the reference current.