Patents by Inventor Chang-gyu Hwang

Chang-gyu Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070148498
    Abstract: Disclosed herein is an ?-Al2O3 coating layer, which is applied on the surface of a cutting tool substrate made of cemented carbide, cermet or ceramic material. The ?-Al2O3 layer is deposited on a TiMewCxNyOz (Me=Zr, Hf, w+x+y+z=1, w, x, y, z?0) layer to a thickness of 2-1 5 ?m through high-temperature chemical vapor deposition, such that the texture coefficient, TC(110), of the crystal plane (110) among the crystal planes (012), (104), (110), (113), (024) and (116) thereof is larger than 1.5, while the texture coefficient of the crystal planes (012), (104), (113), (024) and (116) is smaller than 1.0, said ?-Al2O3 layer having thermal cracks. Thus, the ?-Al2O3 layer has improved abrasion resistance and adhesion.
    Type: Application
    Filed: November 3, 2006
    Publication date: June 28, 2007
    Inventors: Geun-Woo PARK, Chang-Gyu Hwang, Yong-Hee Choi
  • Patent number: 5858833
    Abstract: Integrated circuit memory devices are manufactured by forming spaced apart source and drain regions in an integrated circuit substrate, and an insulated gate on the integrated circuit substrate therebetween. An interlayer insulating layer is formed on the integrated circuit substrate, including first and second conductive pad contacts which extend therethrough and which electrically contact the source and the drain region, respectively. A trench is formed in the interlayer insulating layer, including in the second conductive pad contact. A first insulating layer is formed to line the trench, except for adjacent the second conductive pad contact. A buried bit line is formed in the trench, electrically contacting the second conductive pad contact through the first insulating layer. A second insulating layer is formed on the first insulating layer and on the buried bit line, except for adjacent the first conductive pad contact.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: January 12, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-seong Lee, Chang-gyu Hwang
  • Patent number: 5405801
    Abstract: A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.
    Type: Grant
    Filed: March 1, 1993
    Date of Patent: April 11, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-man Han, Chang-gyu Hwang, Dug-dong Kang, Young-Jae Choi, Joo-young Yoon
  • Patent number: 5358893
    Abstract: An improved isolation method in a semiconductor device of selective polysilicon oxidation (SEPOX) which can create a field oxide layer having a size below the optical resolution and good isolation characteristics. A buffer layer comprised of polysilicon or amorphous silicon is formed on a semiconductor substrate, and then an anti-oxidative pattern with an opening which defines an isolation region exposing a portion of the buffer layer is formed. Then a portion of the exposed buffer layer is isotropically etched in order to form an undercut portion in the lower portion around the opening. Then an anti-oxidative spacer filling the undercut portion is formed on the sidewall of the opening. Thereafter, a field oxide layer is formed by partially oxidizing the portion of the buffer layer exposed by the opening and the semiconductor substrate exposed in the opening. The size of bird's beak is decreased, thereby forming a field oxide layer with good isolation characteristics and small size.
    Type: Grant
    Filed: September 10, 1993
    Date of Patent: October 25, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-suk Yang, Min-uk Hwang, Chang-gyu Hwang