Patents by Inventor Chang H. Siau
Chang H. Siau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11875861Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.Type: GrantFiled: November 4, 2022Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventors: Chang H. Siau, Hao T. Nguyen
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Patent number: 11861236Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.Type: GrantFiled: May 11, 2022Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
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Patent number: 11791003Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: GrantFiled: October 5, 2022Date of Patent: October 17, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Patent number: 11670346Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.Type: GrantFiled: September 28, 2020Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Chang H. Siau, Michele Piccardi, Qui V. Nguyen
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Publication number: 20230111510Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: December 6, 2022Publication date: April 13, 2023Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
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Publication number: 20230061258Abstract: Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.Type: ApplicationFiled: April 11, 2022Publication date: March 2, 2023Inventors: Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa, Chang H. Siau
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Publication number: 20230068580Abstract: A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.Type: ApplicationFiled: February 15, 2022Publication date: March 2, 2023Inventors: Chang H. Siau, Jonathan S. Parry
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Publication number: 20230046283Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.Type: ApplicationFiled: November 4, 2022Publication date: February 16, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Chang H. Siau, Hao T. Nguyen
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Publication number: 20230022858Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: ApplicationFiled: October 5, 2022Publication date: January 26, 2023Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Publication number: 20220415794Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventors: Qui V. Nguyen, Chang H. Siau
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Patent number: 11537484Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: GrantFiled: August 6, 2021Date of Patent: December 27, 2022Assignee: Micron Technology, Inc.Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
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Patent number: 11508444Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.Type: GrantFiled: March 12, 2021Date of Patent: November 22, 2022Assignee: Micron Technology, Inc.Inventors: Chang H. Siau, Hao T. Nguyen
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Patent number: 11488677Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: GrantFiled: December 10, 2020Date of Patent: November 1, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Patent number: 11437318Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.Type: GrantFiled: June 12, 2020Date of Patent: September 6, 2022Assignee: Micron Technology, Inc.Inventors: Qui V. Nguyen, Chang H. Siau
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Publication number: 20220276806Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.Type: ApplicationFiled: May 11, 2022Publication date: September 1, 2022Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
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Publication number: 20220208283Abstract: Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.Type: ApplicationFiled: March 12, 2021Publication date: June 30, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Chang H. Siau, Hao T. Nguyen
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Publication number: 20220189570Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
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Patent number: 11354067Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.Type: GrantFiled: August 5, 2020Date of Patent: June 7, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Kalyan Chakravarthy C. Kavalipurapu, Chang H. Siau, Shigekazu Yamada
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Publication number: 20220066894Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).Type: ApplicationFiled: August 6, 2021Publication date: March 3, 2022Inventors: Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee, Chang H. Siau
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Publication number: 20220068325Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.Type: ApplicationFiled: September 28, 2020Publication date: March 3, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Chang H. Siau, Michele Piccardi, Qui V. Nguyen