Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Abstract: A semiconductor structure includes a p-type metal-oxide semiconductor (PMOS) region and an n-type metal-oxide semiconductor (NMOS) region, first source/drain (S/D) features in the PMOS region and second S/D features in the NMOS region, a first channel region connecting the first S/D features and a second channel region connecting the second S/D features, a first high-k metal gate stack (HKMG) over the first channel region and a second HKMG over the second channel region, first gate spacers on sidewalls of the first HKMG and second gate spacers on sidewalls of the second HKMG, a first etch-stop layer (ESL) on the first S/D features and the first gate spacers and a second ESL on the second S/D features and the second gate spacers, an oxide layer on the first ESL but not the second ESL, and an interlayer dielectric (ILD) layer on the oxide layer and the second ESL.

Abstract: The disclosure provides a quantum device and a microwave device. The quantum device includes a first partition, a second partition, an upper circuit board, a lower circuit board and a flexible circuit. The second partition is arranged below the first partition. The first partition and the second partition are used to define an ultra-low temperature chamber of the quantum device. The upper circuit board, the lower circuit board and the flexible circuit are arranged in the ultra-low temperature chamber. The upper circuit board is disposed on a lower surface of the first partition. The lower circuit board is disposed on an upper surface of the second partition. The flexible circuit is electrically connected between the upper circuit board and the lower circuit board to provide multiple signal paths for mutual signal transmission between the upper circuit board and the lower circuit board.

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a cached mapping table area and has a root mapping table. The processor determines whether a first node mapping table of the node mapping tables is temporarily stored in the cached mapping table area according to the root mapping table. In response to the first node mapping table is temporarily stored in the cached mapping table area, the processor accesses data according to the first node mapping table in the cached mapping table area, marks the modified first node mapping table through an asynchronous index identifier, and writes back the modified first node mapping table from the cached mapping table area to the memory array.

Abstract: A mobile signal light set is disclosed to include three warning signal bars collapsibly arranged on a base to form a light-emitting warning triangle, which base holding a dry battery and a rechargeable battery on the inside, a lamp bulb at one end, a battery charging/discharging control switch, a warning signal bar on/off switch for controlling on/off status of the LEDs of the warning signal bars, a lamp bulb on/off switch for controlling on/off status of the lamp bulb, a cable with AC adapter connector for converting city power supply into AC power supply for charging the rechargeable battery, a cable with car DC connector connectable to the socket for cigarette lighter of a car for charging the battery of the car with the battery power supply of the rechargeable battery or charging the rechargeable battery with the battery of the car subject to the control of the battery charging/discharging control switch.

Abstract: A mobile signal light set is disclosed to include three warning signal bars collapsibly arranged on a base to form a light-emitting warning triangle, which base holding a dry battery and a rechargeable battery on the inside, a lamp bulb at one end, a battery charging/discharging control switch, a warning signal bar on/off switch for controlling on/off status of the LEDs of the warning signal bars, a lamp bulb on/off switch for controlling on/off status of the lamp bulb, a cable with AC adapter connector for converting city power supply into AC power supply for charging the rechargeable battery, a cable with car DC connector connectable to the socket for cigarette lighter of a car for charging the battery of the car with the battery power supply of the rechargeable battery or charging the rechargeable battery with the battery of the car subject to the control of the battery charging/discharging control switch.

Abstract: A multipurpose mosquito trap lamp base includes a base that admits light, a holder frame mounted in the base and holds an induced-draft fan at the front side and an ultraviolet lamp at the rear side, a hollow shell coupled to the rear side of the base for trapping mosquitoes, a filter cap capped on the rear side of the hollow shell for removing dust from air passing through the hollow shell, and an ozone generator mounted inside the base for generating ozone to sterilize air passing through the base and the hollow shell and the filter cap.

Abstract: A multipurpose mosquito trap lamp base includes a base that admits light, a holder frame mounted in the base and holds an induced-draft fan at the front side and an ultraviolet lamp at the rear side, a hollow shell coupled to the rear side of the base for trapping mosquitoes, a filter cap capped on the rear side of the hollow shell for removing dust from air passing through the hollow shell, and an ozone generator mounted inside the base for generating ozone to sterilize air passing through the base and the hollow shell and the filter cap.