Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

Abstract: A light emitting device includes a first semiconductor layer of a first conductivity type, an active layer adjacent to the first semiconductor layer, a second semiconductor layer of a second conductivity type and provided adjacent to the active layer, and a passivation layer provided on a side surface of the active layer. The passivation layer may be a semiconductor layer of one of the first conductivity type, the second conductivity type or a first undoped semiconductor layer. A first electrode may be coupled to the first semiconductor layer and a second electrode may be coupled to the second semiconductor layer.

Abstract: Provided are a light emitting device, a light emitting device package and a lighting system including the same. The light emitting device (LED) comprises a light emitting structure comprising a second conductive type semiconductor layer, an active layer, and a first conductive type semiconductor layer and a first electrode over the light emitting structure. A portion of the light emitting structure is sloped at a predetermined angle.

Abstract: Disclosed are a light emitting device having at least one air bar capable of improving light extracting efficiency and a method of manufacturing the same. With the present invention, there is provided a method of manufacturing a light emitting device including a semiconductor layer(s) having an air-bar layer(s) with a plurality of air bars. The method includes at least one process cycle for forming the semiconductor layer(s). The process cycle includes: forming a patterning thin-film layer on a substrate or a thin-film layer; forming on the patterning thin-film layer an etching guide pattern and an air-bar pattern connected to the etching guide pattern; forming a semiconductor layer(s) on the patterns and exposing the etching guide pattern; wet-etch the exposed etching guide pattern by using a wet-etching solution; and etch the air-bar pattern connected to the etching guide pattern.

Abstract: Techniques and circuits for ensuring one or more circuit components are not subjected to voltage levels above their rated voltage tolerance due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals used to program a voltage regulator. In response to determining the core logic voltage supply is below a predetermined level, the sense circuit may generate one or more regulated voltage signals to override regulated voltage signals generated by the voltage regulator.

Abstract: Embodiments for providing a plurality of bias voltages to input/output circuitry are disclosed.

Abstract: Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage supply sense circuit may monitor a level of a voltage supply that powers core logic that generates control signals to be driven on I/O pads. The sense circuit may generate one or more control signals used to keep I/O pads in a high impedance state.

Abstract: A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

Abstract: A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

Abstract: A semiconductor memory architecture for embedded memory instances having redundancy. A fuse box register is provided outside the memory macro associated with the memory instances. The memory instances are daisy-chained to the fuse box register containing a plurality of fuses used for storing fuse data associated with the defective rows and columns of main memory. During power-up or after blowing the fuses, the contents of the fuses (i.e., fuse data) are transferred to a plurality of volatile redundancy scan flip-flops. The fuse box is then deactivated to eliminate quiescent current through the fuses. The redundancy scan flip-flops, connected in a scan chain, are located inside the fuse box as well as the memory instances. During the shifting mode of operation, the fuse contents are scanned into individual flip-flops, organized as scan registers for row redundancy and column redundancy, of the memory instances.

Abstract: Method for forming a single crystal GaN semiconductor substrate and a GaN diode with the substrate is disclosed which forms in a short time period, has a low crystal defect concentration and allows forming a size large enough to fabricate an optical device, the method including either the steps of fast growth of a GaN group material on an oxide substrate to a thickness without cracking and subjecting to mechanical polish to remove a portion of the oxide substrate, and growing GaN again on the grown GaN layer and complete removal of the remaining oxide substrate to obtain a GaN film, or the steps of separating the oxide substrate from the GaN layer utilizing cooling to obtain a GaN film, grown GaN on the GaN film to a predetermined thickness to form a GaN bulk single crystal and mirror polishing it to form the GaN single crystal substrate, whereby a defectless GaN single crystal substrate of a size required for fabrication of an optical device can be obtained within a short time period because fast homoeptaxia

Abstract: A switching circuit for switching between a main power supply and a battery power supply includes a comparator, a p-channel battery power transfer transistor, a p-channel main power transfer transistor and an inverter. The comparator operates on the main power supply and is connected on input to the main power supply and to the battery power supply. The comparator compares the voltage level of the main power supply with the voltage level of the battery power supply and provides a selection signal which is low when the voltage level of the battery power supply is higher than the voltage level of the main power supply. The p-channel battery power transfer transistor is controlled by the selection signal and transfers the battery supply signal to a switched power supply node. The inverter operates on the battery power supply and inverts the voltage level of the selection signal.

Abstract: The present invention is a battery backed output buffer which provides a well-defined signal, even during battery power. The buffer includes a regular output buffer for providing output data during operation with a main power supply and for switching to a tri-state during battery power. The buffer also includes a configurable battery backed output buffer which provides a predetermined output signal during battery operation and produces a signal in the tri-stated during main power operation.

Abstract: A unit for maintaining the value of information regarding the state of a device during battery power includes one local latch per bit of state to be maintained. The latch is powered by a switched power supply which switches between main and battery power supplies. The latch latches the value of the bit of state when the value of the bit of state is valid and the power of the device is significant and maintains the value otherwise, typically during battery operation.