Abstract: Disclosed herein is a multifunctional therapeutic device with educational and entertainment functions, including a body including a program engine and a power supply unit. The multifunctional therapeutic device includes a data storage unit, an image display unit, and a sound output unit. The data storage unit is removably mounted on the body, is electrically connected to the program engine, and temporarily stores image and sound output data. The image display unit is mounted on the remaining side of the body so that its angle can be adjusted, is electrically connected to the program engine, and outputs an image through the program engine. The sound output unit is mounted between the data storage unit and the image display unit, is electrically connected to the program engine, and outputs a sound through the program engine. The image display unit and the sound output unit are operated separately or in combination.

Abstract: Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.

Abstract: A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

Abstract: An encryption/decryption apparatus and method using an advanced encryption standard (AES) Rijndael algorithm are provided. The apparatus includes a round key operator that performs arithmetic operations on a round key for a first round and first partial round keys of round keys for second to last rounds and generates the round keys for the second to last rounds, and a round executor that performs an encryption or decryption operation using the round key for the first round and the round keys for the second to last rounds.

Abstract: A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.

Abstract: A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital logic value onto an input lead of the discharge circuit. In this way, the sense amplifiers share the discharge circuit. In one example, the memory includes a pair of differential read lines that are precharged to begin a read operation. After precharging, if either of two sense amplifiers is enabled and outputting the first digital logic value, then a first discharge circuit discharges a first of the global read lines. If either of two sense amplifiers is enabled and outputting the second digital logic value, then a second discharge circuit discharges a second of the global read lines.

Abstract: A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells.

Abstract: A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

Abstract: A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling of the dummy word line. The dummy bit line matures at a same rate that a real bit line matures. The method also includes disabling the dummy word line in response to determining a threshold voltage differential based on monitoring maturation of the dummy bit line. The real word line is enabled a predefined delay after enabling of the dummy word line. Similarly, the word line is disabled the predefined delay after disabling of the dummy word line. In response to disabling the dummy word line, a sense enable signal is generated.

Abstract: A memory has a novel self-timing circuit that generates internal memory control signals. Control signals may include an address latch enable signal, a decoder enable signal, and a sense amplifier enable signal. The circuit has a timing loop whose timing mimics the timing of an access of the real memory. The timing loop includes dummy bit cells of identical construction to bit cells in the real array being accessed, a programmable delay circuit, and a programmable accelerator circuit. The dummy bit cells cause the timing of the control signals to track speed changes in the memory array being accessed. The programmable delay and accelerator circuits are usable to slow or speed the timing loop. The programmable delay and accelerator circuits are usable to achieve a desired yield to memory access speed tradeoff. Flexibility of the timing loop allows a memory to be designed before memory access timing characteristics are fixed.

Abstract: A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells.

Abstract: Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.

Abstract: Techniques for reducing leakage current in memory arrays are described. A memory array has multiple rows and multiple columns of memory cells. Bit lines are coupled to the columns of memory cells, and word lines are coupled to the rows of memory cells. The bit lines have disconnected paths to a power supply and float during a sleep mode for the memory array. The bit lines may be coupled to (i) precharge circuits used to precharge the bit lines prior to each read or write operation, (ii) pass transistors used to couple the bit lines to sense amplifiers for read operations, and (iii) pull-up transistors in drivers used to drive the bit lines for write operations. The precharge circuits, pass transistors, and pull-up transistors are turned off during the sleep mode. The word lines are set to a predetermined logic level to disconnect the memory cells from the bit lines during the sleep mode.

Abstract: A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital logic value onto an input lead of the discharge circuit. In this way, the sense amplifiers share the discharge circuit. In one example, the memory includes a pair of differential read lines that are precharged to begin a read operation. After precharging, if either of two sense amplifiers is enabled and outputting the first digital logic value, then a first discharge circuit discharges a first of the global read lines. If either of two sense amplifiers is enabled and outputting the second digital logic value, then a second discharge circuit discharges a second of the global read lines.

Abstract: A memory has a novel self-timing circuit that generates internal memory control signals. Control signals may include an address latch enable signal, a decoder enable signal, and a sense amplifier enable signal. The circuit has a timing loop whose timing mimics the timing of an access of the real memory. The timing loop includes dummy bit cells of identical construction to bit cells in the real array being accessed, a programmable delay circuit, and a programmable accelerator circuit. The dummy bit cells cause the timing of the control signals to track speed changes in the memory array being accessed. The programmable delay and accelerator circuits are usable to slow or speed the timing loop. The programmable delay and accelerator circuits are usable to achieve a desired yield to memory access speed tradeoff. Flexibility of the timing loop allows a memory to be designed before memory access timing characteristics are fixed.

Abstract: A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

Abstract: A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.

Abstract: Since a welding apparatus according to an exemplary embodiment of the present invention is formed to radiate a laser beam at at least one position in at least one direction, a working hour may be reduced and productivity may be increased when a welding operation is performed by using the welding apparatus according to the exemplary embodiment of the present invention.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: An apparatus and method for processing a paging in a WCDMA terminal realize a hardware device for checking whether or not there is a page by interpreting a PICH and an SCCPCH according to a DXR cycle. When a page is detected by this device, a digital base band unit (DBB) is turned on to analyze a PI (paging indicator) of the PICH and a MAC header of the SCCPCH. Therefore, there is no need to operate the DBB at every DXR cycle to check for a page, and thereby the processing loads of the DBB and power consumption of the WCDMA terminal can be reduced significantly.