Patents by Inventor Chang Ho Maeng

Chang Ho Maeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10090402
    Abstract: The method includes steps for improving gate cut isolation region critical dimension (CD) control. Prior to replacement metal gate (RMG) formation, a first sacrificial gate adjacent to first and second channel regions and made of a first sacrificial material (e.g., polysilicon or amorphous silicon) is replaced with a second sacrificial gate made of a second sacrificial material (e.g., amorphous carbon) that is more selectively and anisotropically etchable. A cut is made, dividing the second sacrificial gate into first and second sections, and the cut is then filled with a dielectric to form the gate cut isolation region. The second sacrificial material ensures that, when an opening in a mask pattern used to form the cut extends over a gate sidewall spacer and interlayer dielectric (ILD) material, recesses are not form within the spacer or ILD. Thus, the CD of the isolation region can be controlled.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Chang Ho Maeng, Pei Liu, Junsic Hong, Laertis Economikos, Ruilong Xie
  • Patent number: 10056458
    Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Ho Maeng, Andy Wei, Anthony Ozzello, Bharat Krishnan, Guillaume Bouche, Haifeng Sheng, Haigou Huang, Huang Liu, Huy M. Cao, Ja-Hyung Han, SangWoo Lim, Kenneth A. Bates, Shyam Pal, Xintuo Dai, Jinping Liu
  • Patent number: 9922972
    Abstract: A lithography method and accompanying structure for decreasing the critical dimension (CD) and improving the CD uniformity within semiconductor devices uses a layer of silicon carbide as an embedded blocking mask for defining semiconductor architectures, including contact trench openings to form trench silicide contacts.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaofeng Qiu, Haigou Huang, Chang Ho Maeng
  • Publication number: 20170200792
    Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Inventors: Chang Ho MAENG, Andy WEI, Anthony OZZELLO, Bharat KRISHNAN, Guillaume BOUCHE, Haifeng SHENG, Haigou HUANG, Huang LIU, Huy M. CAO, Ja-Hyung HAN, SangWoo LIM, Kenneth A. BATES, Shyam PAL, Xintuo DAI, Jinping LIU
  • Publication number: 20170162430
    Abstract: Methods for producing integrated circuits and integrated circuits produced by such methods are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a base dielectric layer overlying a substrate. A sacrificial layer is formed overlying the base dielectric layer, and adjacent conductive components are formed in the sacrificial layer where the adjacent conductive components are physically separated by material of the sacrificial layer. The sacrificial layer is removed such that an air gap is defined between the adjacent conductive components, where the air gap overlies the base dielectric layer. A cap dielectric layer is formed overlying the base dielectric layer and the air gap to enclose the air gap within the integrated circuit.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: Xintuo Dai, Huang Liu, Chang Ho Maeng
  • Publication number: 20160049495
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Applicants: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina TREVINO, Yuan-Hung LIU, Gabriel Padron WELLS, Xing ZHANG, Hoong Shing WONG, Chang Ho MAENG, Taejoon HAN, Gowri KAMARTHY, Isabelle ORAIN, Ganesh UPADHYAYA
  • Patent number: 9252238
    Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: February 2, 2016
    Assignees: LAM RESEARCH CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Kristina Trevino, Yuan-Hung Liu, Gabriel Padron Wells, Xing Zhang, Hoong Shing Wong, Chang Ho Maeng, Taejoon Han, Gowri Kamarthy, Isabelle Orain, Ganesh Upadhyaya
  • Patent number: 9147680
    Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a beveled surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
  • Patent number: 8993445
    Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dae-Han Choi, Dae Geun Yang, Chang Ho Maeng, Wontae Hwang
  • Publication number: 20150024584
    Abstract: Methods for fabricating integrated circuits with reduced replacement metal gate height variability are provided. In an embodiment, a method includes providing a semiconductor substrate with a fin supported thereon and forming a conformal material layer overlying the fin and the semiconductor substrate. A trench is etched within the conformal material layer such that the trench exposes a surface of the fin and the semiconductor substrate. A conductive gate structure is formed within the trench, the conformal material layer is removed, and spacers are formed on the sidewalls of the conductive gate.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Gabriel Padron Wells, Yuan-Hung Liu, Kristina Trevino, Chang Ho Maeng, Taejoon Han
  • Publication number: 20150021694
    Abstract: Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating such integrated circuits are provided. A method includes providing a dielectric layer overlying a semiconductor substrate. The dielectric layer has a first and a second trench. A gate dielectric layer is formed in the first and second trench. A first barrier layer is formed overlying the gate dielectric layer. A work function material layer is formed within the trenches. The work function material layer and the first barrier layer are recessed in the first and second trench. The work function material layer and the first barrier layer form a chamfered surface. The gate dielectric layer is recessed in the first and second trench. A conductive gate electrode material is deposited such that it fills the first and second trench. The conductive gate electrode material is recessed in the first and second trench.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Kristina Trevino, Yuan-Hung Lin, Gabriel Padron Wells, Chang Ho Maeng, Taejoon Han, Hoong Shing Wong
  • Patent number: 8900940
    Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 2, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ashish K. Jha, Tae-Hoon Kim, Tae Hoon Lee, Chang Ho Maeng, Songkram Srivathanakul, Haiting Wang
  • Publication number: 20140199845
    Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Dae-Han CHOI, Dae Geun YANG, Chang Ho MAENG, Wontae HWANG
  • Publication number: 20140193957
    Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.
    Type: Application
    Filed: January 10, 2013
    Publication date: July 10, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ashish K. Jha, Tae-Hoon Kim, Tae Hoon Lee, Chang Ho Maeng, Songkram Srivathanakul, Haiting Wang