Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

Abstract: A method for fabricating a dynamic random access memory is provided. A substrate having two trench capacitors therein is provided, an isolation structure protruding from a surface of the substrate is formed on each trench capacitor, a spacer is formed on the substrate at two sides of each of the isolation structures, and a block layer is formed between each spacer and each isolation structure and between each spacer and the substrate. A trench is formed in the substrate between the trench capacitors, and partial of the trench is located under partial of the spacers and partial of the block layer. The spacers, the block layer, and partial of the isolation structures above the trench are removed. A gate structure protruding from the surface of the substrate is formed in the trench. A doped region is formed in the substrate at each of two sides of the gate structure.

Abstract: A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

Abstract: A method for semiconductor structure formation includes: providing a substrate; forming a first lower mask layer on the substrate; forming a first patterned mask on the first lower mask layer; forming a second lower mask layer on the first lower mask layer and overlaying the first patterned mask; forming a second patterned mask on the second lower mask layer without the second patterned mask overlapping the first patterned mask; etching and undercutting the first lower mask layer and the second lower mask layer to form the third patterned mask with the first patterned mask and the second patterned mask; etching the substrate by using the third patterned mask to form a plurality of islands; and removing the third patterned mask.

Abstract: A method for fabricating a flash memory device including the steps of: providing a substrate having thereon a gate with therein a control gate; lining the substrate and the gate with a liner; forming a silicon layer on the liner; forming a sacrificing layer on the silicon layer; etching the sacrificing layer to expose a portion of the silicon layer; removing the exposed silicon layer to expose a portion of the liner; removing the sacrificing layer; forming a spacer layer on the substrate covering the remaining silicon layer and the exposed liner; etching the spacer layer to form a spacer on sidewall of the gate; and removing the silicon layer that is not covered by the spacer thereby forming floating gate on sidewall of the gate.