Abstract: A deposition mask for manufacturing an organic light emitting display (OLED) using the same are provided. The deposition mask is intended for preventing an organic film from being damaged due to touching of a blocked-off portion of the mask to an emission layer (EML), or chemical transition from being generated at the organic film. For that purpose, the deposition mask stuck to a substrate of the OLED to deposit an organic EML includes an opening and an indentation. The opening is opened so as to deposit the organic EML. The indentation is indented a predetermined depth from a plane facing the substrate.

Abstract: The present invention relates to a method for manufacturing silicon articles for a plasma processing apparatus. The present invention provides a method for manufacturing silicon articles, comprising: preparing a silicon ingot; forming a hollow silicon cylinder and a silicon core cylinder having a diameter less than that of the silicon ingot by coring the silicon ingot; forming a silicon annular plate having a central opening by cutting the hollow silicon cylinder and forming a silicon electrode plate by cutting the silicon core cylinder; and forming a silicon ring by processing the silicon annular plate and forming a silicon electrode by processing the silicon electrode plate. According to the present invention, a hollow silicon cylinder and a silicon core cylinder are manufactured by coring a cylindrical silicon ingot before the silicon ingot is sliced.

Abstract: A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.

Abstract: A semiconductor device includes a pads for receiving a reference voltage and input signals from an external device, a unit gain buffer for receiving the reference voltage as an input, input buffers for identifying a corresponding one of the input signals based on an internal reference voltage outputted from the unit gain buffer, external electrostatic discharge protectors connected to a transmission path of the reference voltage and transmission paths of input signals, and internal electrostatic discharge protectors connected to the transmission path of the reference voltage and the transmission paths of the input signals.

Abstract: An apparatus and method for service band search in a mobile communication terminal are provided. The method includes receiving system information from a Base Station (BS), extracting information identifying a band supporting a network or a service intended for access using the received system information, and searching the identified band for a service band.

Abstract: A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged.

Abstract: A memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, based on the internal clock signal, to ensure reliable writing of data to the memory cells.

Abstract: The present invention relates to an acyclic nucleoside phosphonate derivative which is useful as an antiviral agent (particularly, against hepatitis B virus), pharmaceutically acceptable salts, stereoisomers, and a process for the preparation thereof.

Abstract: A semiconductor memory device includes a pad for receiving an external signal through a first external pin, a reference voltage pad for receiving an external reference voltage through a second external pin, an internal reference voltage generator configured to generate an internal reference voltage using an external voltage in response to a reference voltage select signal, a reference voltage supply unit for generating the reference voltage select signal in response to a plurality of select signals, and selecting one reference voltage between the external reference voltage and the internal reference voltage to output the selected one as a reference voltage, a buffer for converting an output signal of the pad into an internal voltage level on the basis of the reference voltage, and a signal selector for controlling an internal signal to be inputted/outputted through the reference voltage pad in response to the plurality of select signals.

Abstract: Example embodiments of the invention may provide for active baluns. An example active balun may include a resonator that may convert a single-ended input signal to at least two differential input signals, and a differential switching block that includes first and second transistors that each receive a respective one of the at least two differential input signals from the resonator, where the first and second transistors may be cross-coupled to each other to provide a first differential output signal and a second differential output signal. An example active balun may further include one or more loads connected to the first and second differential output signals, and one or more stacked inverters that may provide a first output port and a second output port, where the first output port may be responsive to the first differential output signal and the second output port may be responsive to the second differential output signal.

Abstract: A method and an apparatus for determining validity of a mobile subscriber identifier in a mobile communication terminal are provided. In the method, a temporary identifier assigned from a network is stored in a memory and a SIM card of the terminal. When a network authentication event occurs, the temporary identifier stored in the memory is compared with the temporary identifier stored in the SIM card. An identifier to be transmitted to the network is determined among an International Mobile Subscriber Identity (IMSI) and the temporary identifier stored in the SIM card depending on a result of the comparison.

Abstract: Disclosed are an electrochromic device and a method for fabricating the same. The electrochromic device comprises a transparent electrode, on which an electrochromic layer is formed, a counter electrode on which a reflective layer is formed, and an electrolyte layer interposed between the transparent electrode and the counter electrode. Since the electrolyte layer is formed in only an active region of unit pixels, neither crosstalk nor image diffusion occurs and only the selected region of unit pixels is operated. Thus, the electrochromic device can realize passive matrix displays capable of representing a desired color. Furthermore, the electrochromic device can be utilized in a variety of applications including flexible displays and electrical papers.

Abstract: The invention discloses a transformer for a backlight apparatus including a lamp and a detecting unit. The transformer includes a bobbin, a first winding and a second winding. The bobbin has a low-voltage winding region and a high-voltage winding region. The first winding is wound on the high-voltage winding region and is coupled to the lamp. The low-voltage winding region has a first pin, a second pin and a third pin. Firstly, the second winding is wound on the first pin and then wound on the low-voltage winding region for M turns. Next, the second winding is drawn out from the low-voltage winding region, then wound on the second pin, and then drawn back to be wound on the low-voltage winding region for N turns again. Afterwards, the second winding is drawn out again and wound on the third pin, where each of M and N is a nature number. In addition, the third pin is coupled to the detecting unit.

Abstract: A liquid crystal display (LCD) device includes a first substrate having a plurality of column spacers fixed thereto, a second substrate facing the first substrate, and having a plurality of projections at portions corresponding to the column spacers, the projections contacting the column spacers, and a liquid crystal layer between the first and second substrates.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command and therefore it is possible to implement a simple circuit for the self refresh. A semiconductor memory device includes a self refresh enable signal generator for outputting an activated self refresh enable signal when positive and negative external clock signals are in phase and a de-activated self refresh enable signal when the positive and negative external clock signals are out of phase and a self refresh block for performing a self refresh operation in response to the activated self refresh enable signal.

Abstract: Embodiments of the invention may provide for enhancement systems and methods for a power amplifier output control system. In an example embodiment, driver amplifier control may be provided in conjunction with power amplifier control to improve the power efficiency and/or dynamic range of the transmitter system. Furthermore, control over the driver amplifier may allow for relaxed power control slope, which may lessens the burden of digital to analog converters (DACs) in transmitter systems such as cellular transmitter systems. Also, systems and methods in accordance with example embodiments of the invention may provide a less sensitive solution to operational environment variations such as temperature, battery power voltage and implementation IC process.

Abstract: A gear-shifting structure is provided for a vehicle. The vehicle includes a transmission box that contains therein a gear train, a clutch, a switching fork, a gear-shifting hub, and a motor. The motor cooperates with a worm shaft to actuate the clutching operation of the clutch and to cause movement of the gear-shifting hub in order to carry out the gear shifting operation. The motor has a rotary member that drives the worm shaft on which a worm and a cam are mounted. To effect gear shifting, the motor drives the worm shaft to have the cam abut and displace the clutch and at the same time, the worm drives the gear-shifting hub to thus realize the operation of gear shifting.

Abstract: A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.