Patents by Inventor Chang-Hong HSIEH

Chang-Hong HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791256
    Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: October 17, 2023
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Publication number: 20210066189
    Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong HSIEH
  • Patent number: 10867907
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 15, 2020
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Publication number: 20180323143
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Application
    Filed: July 17, 2018
    Publication date: November 8, 2018
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 10068847
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 4, 2018
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Publication number: 20170194249
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 6, 2017
    Applicants: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Patent number: 9485874
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: November 1, 2016
    Assignees: Industrial Technology Research Institute, Unimicron Technology Corp.
    Inventors: Yu-Hua Chen, Wei-Chung Lo, Dyi-Chung Hu, Chang-Hong Hsieh
  • Publication number: 20140117557
    Abstract: A package substrate and a method for forming the package substrate are disclosed. The package substrate includes an interposer having a plurality of conductive through vias and a first insulating layer formed on the sidewalls of the conductive through vias, a second insulating layer formed on one side of the interposer, and a plurality of conductive vias formed in the second insulating layer and electrically connected to the conductive through vias. By increasing the thickness of the first insulating layer, the face diameter of the conductive through vias can be reduced, and the layout density of the conductive through vias in the interposer can thus be increased.
    Type: Application
    Filed: August 13, 2013
    Publication date: May 1, 2014
    Applicants: UNIMICRON TECHNOLOGY CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Hua CHEN, Wei-Chung LO, Dyi-Chung HU, Chang-Hong HSIEH
  • Publication number: 20140102777
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.
    Type: Application
    Filed: August 26, 2013
    Publication date: April 17, 2014
    Applicants: Unimicron Technology Corporation, Industrial Technology Research Institute
    Inventors: Yu-Hua CHEN, Wei-Chung LO, Dyi-Chung HU, Chang-Hong HSIEH
  • Publication number: 20140084413
    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced.
    Type: Application
    Filed: August 13, 2013
    Publication date: March 27, 2014
    Applicants: UNIMICRON TECHNOLOGY CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Hua CHEN, Wei-Chung LO, Dyi-Chung HU, Chang-Hong HSIEH