Abstract: A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.

Abstract: On-chip delivery of data from an on-chip or off-chip cache is separated into two buses. A fast fill bus provides data to latency critical caches without ECC error detection and correction. A slow fill bus provides the data to latency insensitive caches with ECC error detection and correction. Because the latency critical caches receive the data without error detection, they receive the data at least one clock cycle before the latency insensitive caches, thereby enhancing performance if there is no ECC error. If an ECC error is detected, a software trap is executed which flushes the external cache and the latency sensitive caches that received the data before the trap was generated. If the error is correctable, ECC circuitry corrects the error and rewrites the corrected data back to the external cache. If the error is not correctable, the data is read from main memory to the external cache.