Abstract: An embodiment vehicle door opening/closing system includes an inner panel defining a door open portion of a vehicle, the inner panel including an installation groove having a protruding or recessed shape, a driving device disposed in the installation groove of the inner panel, and a link mechanism installed on a chassis through a rotating shaft, a first end of the link mechanism being connected to the driving device such that power is transferred thereto, and a second end of the link mechanism being connected to a door such that, during driving of the driving device, the link mechanism rotates with reference to the rotating shaft to open/close the door.

Abstract: A pharmaceutical or food composition including alverine, 4-hydroxy alverine, a derivative thereof, or a salt thereof and their uses are disclosed. The composition is useful for preventing, alleviating, or treating muscular weakness-related diseases. When myoblasts are treated with the alverine, 4-hydroxy alverine, derivative thereof, or salt thereof, differentiation into myotubes is promoted. Therefore, the alverine, 4-hydroxy alverine, derivative thereof, or salt thereof can be effectively used in the promotion of differentiation of myoblasts and the prevention, alleviation, or treatment of muscular weakness-related diseases.

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

Abstract: A display device with a touchscreen is provided. The display device includes a display panel having an electrode layer in a display area and a non-display area thereof, and a panel ground layer in the non-display area, and a touchscreen over the display panel and including a touch ground layer having an area overlapping with at least one of the electrode layer and the panel ground layer.

Abstract: A display device with a touchscreen is provided. The display device includes a display panel having an electrode layer in a display area and a non-display area thereof, and a panel ground layer in the non-display area, and a touchscreen over the display panel and including a touch ground layer having an area overlapping with at least one of the electrode layer and the panel ground layer.

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: The present invention relates to a cage assembly for spinal interbody fusion comprising: a main body which is inserted between a vertebral body of a spine from which a disc is removed, and a neighboring vertebral body; a first screw part which is formed on the upper surface of the main body, and which has a spiral shape formed along a first direction heading outward from the center; a second screw part which is formed on the lower surface of the main body, and which has a spiral shape formed along a second direction heading outward from the center; and a space part which is formed to penetrate the upper surface and the lower surface of the main body, and which enables the bones forming the vertebral body and the neighboring vertebral body to fuse together. The purpose of the present invention is to promote the smooth progress of surgery for the bone fusion of two neighboring vertebral bodies, or more than two vertebral bodies, forming the spine.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors, The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

Abstract: The present invention relates to a cage assembly for spinal interbody fusion comprising: a main body which is inserted between a vertebral body of a spine from which a disc is removed, and a neighboring vertebral body; a first screw part which is formed on the upper surface of the main body, and which has a spiral shape formed along a first direction heading outward from the center; a second screw part which is formed on the lower surface of the main body, and which has a spiral shape formed along a second direction heading outward from the center; and a space part which is formed to penetrate the upper surface and the lower surface of the main body, and which enables the bones forming the vertebral body and the neighboring vertebral body to fuse together. The purpose of the present invention is to promote the smooth progress of surgery for the bone fusion of two neighboring vertebral bodies, or more than two vertebral bodies, forming the spine.