Patents by Inventor Chang-Hsi Lin

Chang-Hsi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10083950
    Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
  • Publication number: 20170098639
    Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Larry JANN, Chih-Chien CHANG, Po-Wen CHUANG, Ming-I CHIU, Chang-Hsi LIN, Chih-Chan LI, Yi-Ting HU
  • Patent number: 9536814
    Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
  • Publication number: 20160011627
    Abstract: An input device, protective cover and combination thereof is provided. The protective cover includes a base plate and a plurality of lateral walls, a first positioning portion and a first magnetic portion. The lateral walls are connected to a periphery of the base plate to define an accommodating space for accommodating a mobile device. The first positioning portion is disposed at an outer surface of the base plate The first magnetic portion is disposed at the base plate. The input device includes an input region, a frame region, a second positioning portion and a second magnetic portion. The second positioning portion is disposed at the frame region and detachably engaged with the first positioning portion. The second magnetic portion is disposed at the frame region and magnetically and detachably adhered with the first magnetic portion; thereby, the input device is detachably fastened with the protective cover.
    Type: Application
    Filed: October 31, 2014
    Publication date: January 14, 2016
    Inventor: Chang-Hsi Lin
  • Publication number: 20150243630
    Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Larry JANN, Chih-Chien CHANG, Po-Wen CHUANG, Ming-I CHIU, Chang-Hsi LIN, Chih-Chan LI, Yi-Ting HU
  • Patent number: 7142938
    Abstract: A manufacturing management system and method. The system includes a manufacturing execution system and a plurality of manufacturing sites coupled to the manufacturing execution system. The manufacturing execution system comprises management data to support the manufacturing sites. Each manufacturing site comprises a corresponding site attribute. At least one of the manufacturing sites receives a lot, queries the management data for the lot from the manufacturing execution system according to lot identification and the site attribute of the manufacturing site receiving the lot, and processes the lot accordingly.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: November 28, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiaw-Lin Chi, Kun-Chi Liu, Chien-Wei Wang, Chih-Chien Chang, Chang-Hsi Lin, Chien-Fei Cheng, Lieh-Jung Chen, Fang-Ni Wu, Birgie Kuo, Yi-Fang Su
  • Publication number: 20060079978
    Abstract: A manufacturing management system and method. The system includes a manufacturing execution system and a plurality of manufacturing sites coupled to the manufacturing execution system. The manufacturing execution system comprises management data to support the manufacturing sites. Each manufacturing site comprises a corresponding site attribute. At least one of the manufacturing sites receives a lot, queries the management data for the lot from the manufacturing execution system according to lot identification and the site attribute of the manufacturing site receiving the lot, and processes the lot accordingly.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: Shiaw-Lin Chi, Kun-Chi Liu, Chien-Wei Wang, Chih-Chien Chang, Chang-Hsi Lin, Chien-Fei Cheng, Lieh-Jung Chen, Fang-Ni Wu, Birgie Kuo, Yi-Fang Su
  • Patent number: D743407
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 17, 2015
    Assignee: OZAKI INTERNATIONAL CO. LTD.
    Inventor: Chang-Hsi Lin
  • Patent number: D744492
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: December 1, 2015
    Assignee: OZAKI INTERNATIONAL CO., LTD
    Inventor: Chang-Hsi Lin