Patents by Inventor Chang-Hsiao Lee

Chang-Hsiao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150104938
    Abstract: A method for forming a damascene opening, wherein the method comprises steps as follows: Firstly, a semiconductor structure comprising an inter-metal dielectric (IMD), a first hard mask layer and a second hard mask layer stacked in sequence is provided, wherein the semiconductor structure has at least one trench extending downwards from the second hard mask layer to the IMD. A plasma treatment is then performed to modify a portion of the first hard mask layer exposed from the trench. Subsequently, a wet treatment is performed to remove the second hard mask layer and a portion of the first hard mask layer, wherein the plasma-modified portion of the first patterned hard mask layer has a first removing rate substantially less than a second removing rate of the second hard mask layer in the wet treatment.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Fang TAO, Chang-Hsiao LEE, Yu-Fen WANG, Hsin-Yu CHEN
  • Patent number: 8735295
    Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: May 27, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai
  • Publication number: 20130337650
    Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: Chang-Hsiao Lee, Hsin-Yu Chen, Yu-Tsung Lai, Jiunn-Hsiung Liao, Shih-Chun Tsai
  • Patent number: 8592304
    Abstract: A method for filling a metal is disclosed. First, a substrate is provided. The substrate includes a metal material layer, a dielectric layer covering the metal material layer and a hard mask layer covering the dielectric layer. The hard mask layer has at least one opening to expose the underlying dielectric layer. Second, a dry etching step is performed to etch the dielectric layer through the opening to remove part of the dielectric layer to expose the metal material layer and to form a recess and leave some residues in the recess. Then a cleaning step is performed to remove the residues and to selectively remove part of the hard mask to substantially enlarge the opening. Later, a metal fills the recess through the enlarged opening.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: November 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 8277674
    Abstract: A method of removing post-etch residues is provided. First, a substrate is provided. An isolation layer covers the substrate and a conductive layer is embedded in the isolation layer. A dielectric layer and a hard mask cover the isolation layer. Then, an etching process is performed, and a patterned hard mask is formed by etching the hard mask by ions or atoms. After that, a charge-removing process is performed by using a conductive solution to cleaning the patterned hard mask and the dielectric layer so as to remove the charges accumulated on the patterned hard mask and the dielectric layer during the etch process. Finally, the post-etch residues on the patterned hard mask and the dielectric layer is removed.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: October 2, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20120242622
    Abstract: A touch module includes a panel device, an outer frame, and an optical sensor. The panel device includes an array substrate and a display panel having a touch surface. The array substrate is electrically connected to the display panel. The outer frame is disposed on the panel device. The optical sensor is disposed between the panel device and the outer frame, including a wire, at least one lens, a photosensitive chip, and a reflection mirror. The wire is formed on the array substrate. The lens is disposed between the display panel and the outer frame for guiding light transmitted from the touch surface. The photosensitive chip is electrically connected to one end of the wire. The reflection mirror is disposed above the photosensitive chip for reflecting the light guided by the lens to the photosensitive chip.
    Type: Application
    Filed: October 5, 2011
    Publication date: September 27, 2012
    Inventors: Yu Tseng, Po-Fu Huang, Chang-Hsiao Lee
  • Publication number: 20120156885
    Abstract: In a method for processing a semiconductor wafer formed with a copper conductor, the semiconductor wafer is etched in an etching chamber to expose the copper conductor. The etched semiconductor wafer is transmitted from the etching chamber to a buffer zone, where a gas inert to the semiconductor wafer is introduced for a period of time. Then the semiconductor wafer is moved out of the buffer zone to a loading module. Nitrogen is one of the suitable options as the gas, and argon is another option.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Hsiao LEE, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 8137472
    Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: March 20, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Hsiao Lee, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Publication number: 20110250751
    Abstract: A method for filling a metal is disclosed. First, a substrate is provided. The substrate includes a metal material layer, a dielectric layer covering the metal material layer and a hard mask layer covering the dielectric layer. The hard mask layer has at least one opening to expose the underlying dielectric layer. Second, a dry etching step is performed to etch the dielectric layer through the opening to remove part of the dielectric layer to expose the metal material layer and to form a recess and leave some residues in the recess. Then a cleaning step is performed to remove the residues and to selectively remove part of the hard mask to substantially enlarge the opening. Later, a metal fills the recess through the enlarged opening.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Inventors: Chang-Hsiao Lee, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20110244678
    Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Hsiao LEE, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Publication number: 20110139750
    Abstract: A method of removing post-etch residues is provided. First, a substrate is provided. An isolation layer covers the substrate and a conductive layer is embedded in the isolation layer. A dielectric layer and a hard mask cover the isolation layer. Then, an etching process is performed, and a patterned hard mask is formed by etching the hard mask by ions or atoms. After that, a charge-removing process is performed by using a conductive solution to cleaning the patterned hard mask and the dielectric layer so as to remove the charges accumulated on the patterned hard mask and the dielectric layer during the etch process. Finally, the post-etch residues on the patterned hard mask and the dielectric layer is removed.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Inventors: Chang-Hsiao Lee, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20100105205
    Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.
    Type: Application
    Filed: October 27, 2008
    Publication date: April 29, 2010
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Hsiao Lee, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao