Patents by Inventor Changhua Liu
Changhua Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240329333Abstract: Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Intel CorporationInventors: Robert May, Bai Nie, Changhua Liu, Hiroki Tanaka, Kristof Darmawikarta, Lilia May, Shriya Seshadri, Srinivas Pietambaram, Tarek Ibrahim
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Publication number: 20240329339Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a photonic integrated circuit (PIC) having a first surface having a channel and a first magnetic material; a fiber connector including a second surface with a second magnetic material; and a fiber physically coupled to the second surface of the fiber connector by an adhesive material; wherein the first surface of the PIC is coupled to the second surface of the fiber connector by the first and second magnetic materials with the fiber positioned in the channel.Type: ApplicationFiled: March 28, 2023Publication date: October 3, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Changhua Liu, Hiroki Tanaka, Brandon C. Marin, Srinivas V. Pietambaram
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Publication number: 20240219629Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed utilizing photonic integrated circuits with glass cores. An example apparatus comprises a primary package substrate including a glass core and first contacts along an outer surface of the primary package substrate, a photonic integrated circuit (PIC) within the primary package substrate adjacent a surface of the glass core, and a secondary package substrate supporting a semiconductor die on a first side of the secondary package substrate, the secondary package substrate including second contacts on a second side of the secondary package substrate, the first contacts electrically coupled to the second contacts.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Inventors: Changhua Liu, Robert May, Bai Nie
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Publication number: 20240222130Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core. In an embodiment, the TGV comprises a top surface that is non-planar and includes a symmetric ridge on the non-planar top surface.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Shaojiang CHEN, Jeremy D. ECTON, Oladeji FADAYOMI, Hsin-Wei WANG, Changhua LIU, Bin MU, Hongxia FENG, Brandon C. MARIN, Srinivas V. PIETAMBARAM
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Publication number: 20240192453Abstract: An integrated circuit (IC) package substrate comprises an upper surface, a lower surface opposite the upper surface, and an outer side surface extending between the upper surface and the lower surface. At least one optical path is in a plane of the IC package substrate, and at least one vertical optical coupler at an upper or lower surface of the IC package substrate is optically coupled to the optical path.Type: ApplicationFiled: December 9, 2022Publication date: June 13, 2024Applicant: Intel CorporationInventors: Changhua Liu, Robert A. May, Bai Nie
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Publication number: 20240188489Abstract: A cutting mechanism includes a driving device and a cutting device connected with the driving device. The cutting device is configured to execute a cutting task under driving of the driving device, the cutting device includes a plurality of cutting units stacked in a first direction, each cutting unit includes at least one cutting element, and each cutting unit forms a cutting domain when executing the cutting task. In at least one second direction perpendicular to the first direction, a first preset spacing is provided between edges of cutting domains of two cutting units closest to a working surface, and the edge of the cutting domains of the cutting units closer to the working surface of the two cutting units is closer to the driving device than that of the other cutting unit in the second direction.Type: ApplicationFiled: February 16, 2024Publication date: June 13, 2024Inventors: Shiping Jiao, Jiang Du, Xiahong Zha, Changhua Liu, Yangbing Liu
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Publication number: 20240184209Abstract: The present disclosure is directed to a lithographic patterning system including a stage for supporting a substrate with a photo-definable polymer layer, a first actinic radiation source, which is configured to propagate light along a first optical axis, a first mask for patterning the propagated light from the first actinic radiation source, a second actinic radiation source, which is configured to propagate light along a second optical axis, and a second mask for patterning the propagated light from the second actinic radiation source. In a method, first and second propagated lights form an intersection in the photo-definable polymer layer, and a patterned semiconductor component is formed at the intersection.Type: ApplicationFiled: December 1, 2022Publication date: June 6, 2024Inventors: Changhua LIU, Bai NIE, Robert MAY
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Publication number: 20240176070Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include a substrate having a core with a surface, wherein a material of the core includes glass; and a dielectric material on a portion of the surface of the core, the dielectric material including conductive pathways; a photonic integrated circuit (PIC) electrically coupled to the conductive pathways in the dielectric material; a first optical component between the PIC and the surface of the core, wherein the first optical component is coupled to the surface of the core by optical glue or by fusion bonding; and a second optical component coupled to the core, wherein the second optical component is optically coupled to the PIC by an optical pathway through the core and the first optical component.Type: ApplicationFiled: November 28, 2022Publication date: May 30, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Brandon C. Marin, Changhua Liu, Srinivas V. Pietambaram, Hiroki Tanaka
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Publication number: 20240162191Abstract: Embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. The conductive via is directly attached to the conductive trace through the insulative material, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Applicant: Intel CorporationInventors: Jeremy Ecton, Changhua Liu, Brandon C. Marin, Srinivas V. Pietambaram, Mohammad Mamunur Rahman
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Publication number: 20240111090Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Robert A. May, Tarek Ibrahim, Shriya Seshadri, Kristof Darmawikarta, Hiroki Tanaka, Changhua Liu, Bai Nie, Lilia May, Srinivas Pietambaram, Zhichao Zhang, Duye Ye, Yosuke Kanaoka, Robin McRee
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Publication number: 20240113158Abstract: Disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. The substrates may include an anode material, a cathode material, and a conductive material. The anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. The cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. The conductive material may be located at the anode peaks.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Jeremy D. Ecton, Brandon C. Marin, Haobo Chen, Changhua Liu, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20240112972Abstract: Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Hiroki Tanaka, Robert Alan May, Kristof Darmawikarta, Bai Nie, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Changhua Liu
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Publication number: 20240094746Abstract: A multi-machine cooperation method, a scheduling device, and a multi-machine cooperation system are described. The multi-machine cooperation method includes: determining, by a first autonomous robot when detecting an abnormal condition during operation, whether the abnormal condition can be independently processed; and when the abnormal condition cannot be independently processed, sending, by the first autonomous robot, an assistance request to another device in an Internet of Things in which the first autonomous robot is located. In the specification, a multi-machine cooperation operation between autonomous robots or between an autonomous robot and another device can be implemented.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Mingming He, Shuanglong Wu, Don Zhendong Gao, Xiahong Zha, Changhua Liu
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Patent number: 11919907Abstract: Disclosed is a JAK1 and/or JAK2 inhibitor of the following structural formula: or a pharmaceutically acceptable salt thereof. This invention also provides pharmaceutical compositions comprising a compound of Formula (I), optionally including additional therapeutic agents, and use in methods of treatment for hair loss disorders.Type: GrantFiled: May 21, 2021Date of Patent: March 5, 2024Assignee: Sun Pharmaceutical Industries, Inc.Inventors: I. Robert Silverman, Changhua Liu
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Patent number: 11837534Abstract: Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.Type: GrantFiled: December 29, 2017Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Aleksandar Aleksov, Kristof Darmawikarta, Haobo Chen, Changhua Liu, Sri Ranga Sai Boyapati, Bai Nie
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Publication number: 20230236517Abstract: Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Inventors: Changhua LIU, Jianyong MO, Liang ZHANG
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Patent number: 11644757Abstract: Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.Type: GrantFiled: December 19, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Changhua Liu, Jianyong Mo, Liang Zhang
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Publication number: 20230104330Abstract: Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.Type: ApplicationFiled: September 23, 2021Publication date: April 6, 2023Inventors: Jeremy Ecton, Leonel Arana, Whitney Bryks, Haobo Chen, Benjamin Duong, Changhua Liu, Brandon Marin, Srinivas Pietambaram
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Publication number: 20230095281Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Kyle McElhinny, Hongxia Feng, Xiaoying Guo, Steve Cho, Jung Kyu Han, Changhua Liu, Leonel Arana, Rahul Manepalli, Dingying Xu, Amram Eitan
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OPTICAL WAVEGUIDES WITHIN A GLASS SUBSTRATE TO OPTICALLY COUPLE DIES ATTACHED TO THE GLASS SUBSTRATE
Publication number: 20230091050Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to optical interconnects and optical waveguides within a glass layer of a semiconductor package, where dies that are physically and optically coupled with the glass layer are optically coupled with each other via the optical waveguides. One or more reflectors may be used to direct the optical pathway through the glass layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Zhichao ZHANG, Pooya TADAYON, Tarek A. IBRAHIM, Srinivas V. PIETAMBARAM, Changhua LIU, Kemal AYGÜN