Patents by Inventor Chang-Hung Kung
Chang-Hung Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9384996Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.Type: GrantFiled: May 8, 2014Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Kun-Ju Li, Chang-Hung Kung, Yue-Han Wu, Chih-Chien Liu
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Publication number: 20160013100Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.Type: ApplicationFiled: August 17, 2014Publication date: January 14, 2016Inventors: Kun-Ju Li, Po-Cheng Huang, Chih-Chien Liu, Yu-Ting Li, Jen-Chieh Lin, Chang-Hung Kung, Wen-Chin Lin, Chih-Hsun Lin, Kuo-Chin Hung
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Publication number: 20150325574Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Kun-Ju Li, Chang-Hung Kung, Yue-Han Wu, Chih-Chien Liu
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Patent number: 9012300Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.Type: GrantFiled: October 1, 2012Date of Patent: April 21, 2015Assignee: United Microelectronics Corp.Inventors: Wu-Sian Sie, Chun-Wei Hsu, Chia-Lung Chang, Chih-Hsun Lin, Chang-Hung Kung, Yu-Ting Li, Wei-Che Tsao, Yen-Ming Chen, Chun-Hsiung Wang, Chia-Lin Hsu
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Publication number: 20150079780Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.Type: ApplicationFiled: September 13, 2013Publication date: March 19, 2015Applicant: United Microelectronics Corp.Inventors: Yl-Liang Liu, Wu-Sian Sie, Po-Cheng Huang, Chih-Hsien Chen, I-Lun Hung, Yen-Ming Chen, Yu-Ting Li, Chang-Hung Kung, Chun-Hsiung Wang, Chia-Lin Hsu
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Patent number: 8940600Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.Type: GrantFiled: June 3, 2014Date of Patent: January 27, 2015Assignee: United Microelectronics Corp.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Publication number: 20140273371Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.Type: ApplicationFiled: June 3, 2014Publication date: September 18, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Patent number: 8779526Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.Type: GrantFiled: October 28, 2011Date of Patent: July 15, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Patent number: 8765588Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.Type: GrantFiled: September 28, 2011Date of Patent: July 1, 2014Assignee: United Microelectronics Corp.Inventors: Pong-Wey Huang, Chan-Lon Yang, Chang-Hung Kung, Wei-Hsin Liu, Ya-Hsueh Hsieh, Bor-Shyang Liao, Teng-Chun Hsuan, Chun-Yao Yang
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Publication number: 20140106558Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.Type: ApplicationFiled: December 31, 2013Publication date: April 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Yen-Ming Chen, Chia-Hsi Chen, Chang-Hung Kung
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Publication number: 20140094017Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.Type: ApplicationFiled: October 1, 2012Publication date: April 3, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wu-Sian Sie, Chun-Wei Hsu, Chia-Lung Chang, Chih-Hsun Lin, Chang-Hung Kung, Yu-Ting Li, Wei-Che Tsao, Yen-Ming Chen, Chun-Hsiung Wang, Chia-Lin Hsu
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Patent number: 8647986Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.Type: GrantFiled: August 30, 2011Date of Patent: February 11, 2014Assignee: United Microelectronics Corp.Inventors: Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chun-Wei Hsu, Yen-Ming Chen, Chih-Hsun Lin, Chang-Hung Kung
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Patent number: 8643069Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.Type: GrantFiled: July 12, 2011Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Yen-Ming Chen, Chia-Hsi Chen, Chang-Hung Kung
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Patent number: 8513128Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.Type: GrantFiled: June 17, 2011Date of Patent: August 20, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Chang-Hung Kung, Chia-His Chen, Yen-Ming Chen
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Publication number: 20130105912Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
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Publication number: 20130078792Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.Type: ApplicationFiled: September 28, 2011Publication date: March 28, 2013Inventors: Pong-Wey Huang, Chan-Lon Yang, Chang-Hung Kung, Wei-Hsin Liu, Ya-Hsueh Hsieh, Bor-Shyang Liao, Teng-Chun Hsuan, Chun-Yao Yang
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Publication number: 20130052825Abstract: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Inventors: Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chun-Wei Hsu, Yen-Ming Chen, Chih-Hsun Lin, Chang-Hung Kung
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Publication number: 20130015524Abstract: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.Type: ApplicationFiled: July 12, 2011Publication date: January 17, 2013Inventors: Chun-Wei Hsu, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Yen-Ming Chen, Chia-Hsi Chen, Chang-Hung Kung
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Publication number: 20120322265Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Wei HSU, Po-Cheng Huang, Teng-Chun Tsai, Chia-Lin Hsu, Chih-Hsun Lin, Chang-Hung Kung, Chia-His Chen, Yen-Ming Chen