Patents by Inventor Chang-Hwang Hua

Chang-Hwang Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720390
    Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: July 21, 2020
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Yi-Wei Lien
  • Patent number: 10410979
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 10, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Patent number: 10374129
    Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: August 6, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Shu Chen Chen, Huang-Wen Wang, Walter Tony Wohlmuth
  • Publication number: 20190131244
    Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 2, 2019
    Inventors: Chang-Hwang HUA, Yi-Wei LIEN
  • Publication number: 20190096755
    Abstract: An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 28, 2019
    Inventors: Chang-Hwang HUA, Shu Chen CHEN, Huang-Wen WANG, Walter Tony WOHLMUTH
  • Publication number: 20180366417
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer formed on a bottom surface of a compound semiconductor wafer, at least one stress balance layer formed on a bottom surface of the contact metal layer and made of nonconductive material, stress balance layer via holes and a die attachment layer. Each stress balance layer via hole penetrates the stress balance layer. The die attachment layer is made of conductive material, formed on a bottom surface of the stress balance layer and an inner surface of each stress balance layer via hole, and electrically connected with the contact metal layer through the stress balance layer via holes. By locating the stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 20, 2018
    Inventors: Chang-Hwang HUA, Wen CHU
  • Publication number: 20180366913
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer, at least one stress balance layer and a die attachment layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein the at least one stress balance layer is made of at least one conductive material; the die attachment layer is formed on a bottom surface of the at least one stress balance layer, wherein the die attachment layer is made of conductive material. By locating the at least one stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 20, 2018
    Inventors: Chang-Hwang HUA, Wen CHU
  • Publication number: 20180366418
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
    Type: Application
    Filed: April 25, 2018
    Publication date: December 20, 2018
    Inventors: Chang-Hwang HUA, Wen CHU
  • Patent number: 10158212
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer, at least one stress balance layer and a die attachment layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein the at least one stress balance layer is made of at least one conductive material; the die attachment layer is formed on a bottom surface of the at least one stress balance layer, wherein the die attachment layer is made of conductive material. By locating the at least one stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: December 18, 2018
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Patent number: 10096583
    Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 9, 2018
    Assignee: WIN Semiconductos Corp.
    Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
  • Publication number: 20170330843
    Abstract: An advanced moisture resistant structure of compound semiconductor integrated circuit comprises a compound semiconductor substrate, a compound semiconductor epitaxial structure, a compound semiconductor integrated circuit and a moisture barrier layer. The compound semiconductor epitaxial structure is formed on the compound semiconductor substrate. The compound semiconductor integrated circuit is foimed on the compound semiconductor epitaxial structure. The moisture barrier layer is formed on the compound semiconductor integrated circuit. The moisture barrier layer is made of A12O3. The thickness of the moisture barrier layer is greater than or equal to 400 ? and less than or equal to 1000 ? so as to enhance the moisture resistant ability of the compound semiconductor integrated circuit.
    Type: Application
    Filed: August 22, 2016
    Publication date: November 16, 2017
    Inventors: Chang Hwang Hua, Winson Shao
  • Publication number: 20170222011
    Abstract: An improved gate metal structure for compound semiconductor devices comprises sequentially a compound semiconductor substrate, a Schottky barrier layer, an insulating layer and a gate metal. The insulating layer has a gate recess. The surrounding and the bottom of the gate recess are defined by the insulating layer and the Schottky barrier layer respectively. The gate metal includes a contact layer formed on the insulating layer, covering the gate recess and contacted with the Schottky barrier layer at the bottom of the gate recess; a first diffusion barrier layer formed on the contact layer; a second diffusion barrier layer formed on the first diffusion barrier layer; and a conduct layer formed on the second diffusion barrier layer. Thereby the reliability of the compound semiconductor devices is enhanced.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 3, 2017
    Inventors: Chang-Hwang HUA, Kai-Sin CHO, Walter Tony WOHLMUTH
  • Patent number: 9704829
    Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 11, 2017
    Assignee: Win Semiconductor Corp.
    Inventors: Chang-Hwang Hua, Chih-Hsien Lin
  • Publication number: 20170194451
    Abstract: A Schottky barrier semiconductor device having a nanoscale film interface comprises a Schottky barrier layer and a metal electrode; wherein a nanoscale film interface layer is formed on a top surface of the Schottky barrier layer, a thickness of the nanoscale film interface layer is greater than 3 ? and smaller than 20 ?, the nanoscale film interface layer is made of at least one oxide; the metal electrode is formed on the nanoscale film interface layer and contacted with the nanoscale film interface layer.
    Type: Application
    Filed: April 26, 2016
    Publication date: July 6, 2017
    Inventors: Chang-Hwang HUA, Winson SHAO
  • Patent number: 9673186
    Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 6, 2017
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Shinichiro Takatani, Hsien-Fu Hsiao, Cheng-Kuo Lin, Chang-Hwang Hua
  • Publication number: 20170084592
    Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Shinichiro TAKATANI, Hsien-Fu Hsiao, Cheng-Kuo LIN, Chang-Hwang HUA
  • Patent number: 9548276
    Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 17, 2017
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Jason Chen, Chang-Hwang Hua, Wen Chu
  • Publication number: 20160035707
    Abstract: A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Inventors: Chang-Hwang HUA, Chih-Hsien LIN
  • Publication number: 20160020178
    Abstract: An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.
    Type: Application
    Filed: September 29, 2015
    Publication date: January 21, 2016
    Inventors: JASON CHEN, CHANG-HWANG HUA, WEN CHU
  • Patent number: 9190374
    Abstract: A structure of a semiconductor chip with substrate via holes and metal bumps and a fabrication method thereof. The structure comprises a substrate, at least one backside metal layer, at least one first metal layer, at least one electronic device, and at least one metal bump. The substrate has at least one substrate via hole penetrating through the substrate. The at least one first metal layer and electronic device are formed on the front side of the substrate. The at least one metal bump is formed on the at least one first metal layer. The at least one backside metal layer is formed on the backside of the substrate covering the inner surface of the substrate via hole and at least part of the backside of the substrate and connected to the first metal layer on the top of the substrate via hole.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 17, 2015
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Chih-Hsien Lin