Abstract: An organic thin film transistor (OTFT) is disclosed herein. The OTFT has a substrate, a data line, a transfer pad, a source electrode, a drain electrode, an active pattern, a first insulating layer, a gate electrode, a second insulating layer, and a transparent electrode. The data line and the transfer pad are disposed on the substrate. The source electrode and the drain electrode are disposed on the substrate, the data line, and the transfer pad. The active pattern is disposed on the data line, the transfer pad, the substrate, the source electrode, and the drain electrode. With the disposition of the active pattern on the source electrode and the drain electrode, the source electrode and the drain electrode are free from the bombardment of the plasma.

Abstract: An organic thin film transistor (OTFT) is disclosed herein. The OTFT has a substrate, a data line, a transfer pad, a source electrode, a drain electrode, an active pattern, a first insulating layer, a gate electrode, a second insulating layer, and a transparent electrode. The data line and the transfer pad are disposed on the substrate. The source electrode and the drain electrode are disposed on the substrate, the data line, and the transfer pad. The active pattern is disposed on the data line, the transfer pad, the substrate, the source electrode, and the drain electrode. With the disposition of the active pattern on the source electrode and the drain electrode, the source electrode and the drain electrode are free from the bombardment of the plasma.

Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Abstract: The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

Abstract: The present invention provides a TFT substrate and a liquid crystal display panel using the TFT substrate. The TFT substrate includes: first and second sharing capacitors (2, 4) that are connected in parallel. The first sharing capacitor (2) includes a first upper substrate (22), a first lower substrate (24) opposite to the first upper substrate (22), and a first semiconductor layer (26) arranged between the first upper substrate (22) and the first lower substrate (24). The second sharing capacitor (4) includes a second upper substrate (42), a second lower substrate (44) opposite to the second upper substrate (42), and a second semiconductor layer (46) arranged between the second upper substrate (42) and the second lower substrate (44). The first upper substrate (22) of the first sharing capacitor (2) and the second lower substrate (44) of the second sharing capacitor (4) are electrically connected to the pixel electrode (6).