Abstract: An array substrate including a substrate having a pixel region, a gate line and a gate electrode on the substrate, the gate electrode being connected to the gate line, a gate insulating layer on the gate line and the gate electrode, an oxide semiconductor layer on the gate insulating layer, an auxiliary pattern on the oxide semiconductor layer, and source and drain electrodes on the auxiliary pattern, the source and drain electrodes being disposed over the auxiliary pattern and spaced apart from each other to expose a portion of the auxiliary pattern, the exposed portion of the auxiliary pattern exposing a channel region and including a metal oxide over the channel region, wherein a data line crosses the gate line to define the pixel region and is connected to the source electrode, a passivation layer on the source and drain electrodes and the data line.