Patents by Inventor Chang-jip Yang
Chang-jip Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6953739Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.Type: GrantFiled: November 12, 2003Date of Patent: October 11, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jip Yang, Chan-hee Han, Young-kyou Park, Jae-wook Kim
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Publication number: 20040094091Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.Type: ApplicationFiled: November 12, 2003Publication date: May 20, 2004Inventors: Chang-Jip Yang, Chan-Hee Han, Young-Kyou Park, Jae-Wook Kim
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Patent number: 6683010Abstract: A semiconductor device provides improved performance at high integration levels by utilizing a gate insulation layer formed from silicon-oxynitride which prevents impurities in the doped gate electrode from diffusing into the semiconductor substrate during the fabrication processes. A method for forming the silicon-oxynitride layer utilizes a vertical diffusion furnace to increase productivity and achieve a uniform nitrogen density in the silicon-oxynitride layer. The method includes forming an initial oxide layer on a semiconductor substrate, changing the initial oxide layer into a pure oxide layer, and then changing the pure oxide layer into a silicon-oxynitride layer. The initial oxide layer is formed by loading a semiconductor substrate into a diffusion furnace at a temperature between 550˜750° C., raising the temperature of the substrate to between 700˜950° C., and injecting a mixture of oxygen and nitrogen has into the diffusion furnace.Type: GrantFiled: June 25, 1998Date of Patent: January 27, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Baek-gyun Lim, Eu-seok Kim, Chang-jip Yang, Young-kyou Park
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Patent number: 6673673Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.Type: GrantFiled: March 6, 2000Date of Patent: January 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jip Yang, Chan-hee Han, Young-kyou Park, Jae-wook Kim
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Patent number: 6423998Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.Type: GrantFiled: June 1, 1999Date of Patent: July 23, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-ho Hyun, Byung-soo Koo, Wook-sung Son, Chang-jip Yang
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Patent number: 6323084Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.Type: GrantFiled: October 19, 1999Date of Patent: November 27, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-ho Hyun, Byung-soo Koo, Wook-sung Son, Chang-jip Yang
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Patent number: 6312987Abstract: A method for forming a hemispherical grain polysilicon layer on an amorphous silicon film increases the surface area of the layer by first forming silicon crystal nuclei on the film, and then enlarging the nuclei before annealing. The nuclei are formed on the amorphous silicon film loading a substrate having the amorphous silicon film into a chamber and injecting a silicon source gas into the chamber at a first, low flow rate which allows the pressure of the chamber to be reduced, thereby increasing the density of the crystal nuclei. A silicon source gas is then injected into the chamber at a second, higher flow rate, thereby enlarging the silicon crystal nuclei on the amorphous layer. The resulting structure is then annealed to form a hemispherical grain polysilicon layer having a large surface area due to the irregular surface of the polysilicon layer.Type: GrantFiled: May 1, 1998Date of Patent: November 6, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hee Han, Young-ho Kang, Chang-jip Yang, Young-kyou Park
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Patent number: 6090188Abstract: An air intake apparatus for semiconductor fabricating equipment reduces the inflow of chemical contaminants, such as ozone (O.sub.3), into the equipment. The air intake apparatus includes a fan as an air intake device, and a chemical filter containing activated carbon to remove the chemical contaminants from air drawn in from outside the equipment. The air intake apparatus may further include first and second filters for removing particulate contaminants from the air. By applying the air intake apparatus to chemical vapor deposition (CVD) equipment used to carry out a process for forming hemispherical grains (HSGs), which is sensitive to a native oxide layer, the ozone density inside the CVD equipment is decreased. Accordingly, the semiconductor device produced has a higher capacitance and enhanced performance.Type: GrantFiled: September 29, 1998Date of Patent: July 18, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jip Yang, Geun-mok Youk, Chong-hyeong Cho, Young-kyou Park
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Patent number: 6074486Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.Type: GrantFiled: April 20, 1998Date of Patent: June 13, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jip Yang, Chan-hee Han, Young-kyou Park, Jae-wook Kim
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Apparatus for guiding air current in a wafer loading chamber for chemical vapor deposition equipment
Patent number: 6036781Abstract: An air current guiding apparatus includes a plurality of dampers installed on a filter unit on an inner wall of air supply unit for blowing clean air over wafers loaded in a boat for transfer to a reaction chamber for chemical vapor deposition. Each of the dampers has a certain length and angular orientation to force the air in a designated direction so that the air current in a wafer loading chamber maintains an appropriate velocity and is free from air turbulence, thereby minimizing the number of contaminating particles in the wafer loading chamber.Type: GrantFiled: March 19, 1997Date of Patent: March 14, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Yo-han Ahn, Jin-chul Yoon, Chang-jip Yang, Ho-wang Kim -
Patent number: 5821152Abstract: A method of forming a hemispherical grained silicon electrode includes the steps of forming an amorphous silicon layer on an integrated circuit substrate, and heating the integrated circuit substrate and the amorphous silicon layer to a first deposition temperature. The amorphous silicon layer is exposed to a source gas including silicon while maintaining the first deposition temperature thereby forming silicon crystal nuclei on a surface of the amorphous silicon layer. The temperature of the integrated circuit substrate is lowered to a second deposition temperature wherein the second deposition temperature is less than the first deposition temperature. The silicon crystal nuclei are exposed to the source gas including silicon while maintaining the second deposition temperature thereby increasing a size of the silicon crystal nuclei.Type: GrantFiled: October 15, 1997Date of Patent: October 13, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hee Han, Chang-jip Yang, Young-kyou Park, Jae-wook Kim
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Patent number: 5470611Abstract: In a method for forming a compound oxide film such as a gate oxide film of a MOS device, after a first oxide film (such as a HTO film) is formed on a semiconductor substrate by deposition at a high temperature, a second oxide film is formed below the first oxide film by wet oxidizing the surface of the semiconductor substrate, which results in a compound oxide film consisting of the HTO film and the wet oxide film. Therefore, a high quality oxide film having excellent electrical characteristics can be formed.Type: GrantFiled: November 10, 1994Date of Patent: November 28, 1995Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jip Yang, Jun-gyo Jung
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Patent number: 5352293Abstract: The present invention relates to a tube apparatus for manufacturing a semiconductor device, comprising a one-piece cylindrical tube having a door for loading a semiconductor wafer. One end of the tube is closed and two openings are formed adjacent thereto. The other end is conical and has an opening formed in the apex thereof. A saddle having two openings is mounted on the tube so that the two openings of the saddle correspond to the two openings of the tube which are adjacent to the closed end. Using the tube apparatus enhances the efficiency of a diffusion process. Contaminant residue does not remain in the process tube because the temperature therein is more uniform over the length of the tube, compared to a conventional apparatus. The tube can therefore be used semi-permanently.Type: GrantFiled: January 6, 1993Date of Patent: October 4, 1994Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jip Yang, Kyu-bok Ryu, Jung-soo An, Jun-geen An