Patents by Inventor Chang-Ju Choi
Chang-Ju Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970090Abstract: A railess variable seatback type rear seat includes: a linear movement device configured to convert a rotation of a motor into a linear movement; a sliding movement device configured to convert the linear movement into a sliding movement in which a seat cushion is pushed forward or backward; and a reclining angle change device configured to convert the sliding movement into a reclining movement, and to fold a seatback, which is connected to the seat cushion, forward or to recline the seatback backward.Type: GrantFiled: July 20, 2021Date of Patent: April 30, 2024Assignees: HYUNDAI MOTOR COMPANY, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.Inventors: Seung-Hyun Kim, Sang-Hyun Lee, Min-Ju Lee, Byung-Yong Choi, Chan-Ho Jung, Seon-Chae Na, Young-Woon Choi, Jae-Jin Lee, Dong-Hwan Kim, In-Chang Hwang
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Publication number: 20240109397Abstract: A method for controlling an electric heater of a vehicular heating, ventilation, and air conditioning (HVAC) system includes turning on the electric heater; determining whether an ambient air temperature of a vehicle is higher than or equal to a threshold ambient air temperature, and a battery temperature is lower than or equal to a threshold battery temperature; determining whether battery efficiency is lower than or equal to threshold efficiency when the ambient air temperature of the vehicle is higher than or equal to the threshold ambient air temperature, and the battery temperature is lower than or equal to the threshold battery temperature; and turning off the electric heater when the battery efficiency is lower than or equal to the threshold efficiency, wherein the electric heater is configured to receive electric energy from the battery.Type: ApplicationFiled: March 30, 2023Publication date: April 4, 2024Inventors: Dae Hyun Song, Chang Gi Ryu, Woo Jin Lee, Dong Ju Ko, Hyun Hun Choi, Chun Kyu Kwon, In Uk Ko
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Publication number: 20240086603Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: In HUH, Jeong-hoon KO, Hyo-jin CHOI, Seung-ju KIM, Chang-wook JEONG, Joon-wan CHAI, Kwang-II PARK, Youn-sik PARK, Hyun-sun PARK, Young-min OH, Jun-haeng LEE, Tae-ho LEE
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Patent number: 11300885Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.Type: GrantFiled: July 25, 2018Date of Patent: April 12, 2022Assignee: Intel CorporationInventors: Robert Bristol, Guojing Zhang, Tristan Tronic, John Magana, Chang Ju Choi, Arvind Sundaramurthy, Richard Schenker
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Publication number: 20200033736Abstract: Embodiments described herein comprise extreme ultraviolet (EUV) reticles and methods of forming EUV reticles. In an embodiment, the reticle may comprise a substrate and a mirror layer over the substrate. In an embodiment, the mirror layer comprises a plurality of alternating first mirror layers and second mirror layers. In an embodiment, a phase-shift layer is formed over the mirror layer. In an embodiment, openings for printable features and openings for non-printable features are formed into the phase-shift layer. In an embodiment, the non-printable features have a dimension that is smaller than a dimension of the printable features.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Inventors: Robert BRISTOL, Guojing ZHANG, Tristan TRONIC, John MAGANA, Chang Ju CHOI, Arvind SUNDARAMURTHY, Richard SCHENKER
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Publication number: 20190025694Abstract: Approaches for fabricating a lithographic mask are described. In an example, a lithographic mask for patterning semiconductor circuits includes a substrate. An in-die region is disposed on the substrate. The in-die region includes a patterned shifter material in direct contact with the substrate. The patterned shifter material includes features having sidewalls. A frame region is disposed on the substrate and surrounding the in-die region. The frame region includes an absorber layer in direct contact with the substrate.Type: ApplicationFiled: March 31, 2016Publication date: January 24, 2019Inventor: Chang Ju CHOI
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Patent number: 8679706Abstract: Techniques are disclosed for enhancing critical dimension (CD) resolution in photomask processing. In some cases, the techniques can be implemented, for instance, to enhance space and line pattern resolution independently on a given phase-shifting photomask (PSM). The disclosed techniques can be implemented, for example, to extend existing photolithography techniques/technologies (e.g., 193 nm photolithography) to additional process nodes. For instance, some embodiments can be used to produce extremely high-resolution photomasks which generate features having sizes in the 10 nm node and beyond. The disclosed techniques can be implemented in the fabrication of a wide range of integrated circuits (ICs) and other devices.Type: GrantFiled: July 30, 2012Date of Patent: March 25, 2014Assignee: Intel corporationInventor: Chang Ju Choi
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Publication number: 20140030638Abstract: Techniques are disclosed for enhancing critical dimension (CD) resolution in photomask processing. In some cases, the techniques can be implemented, for instance, to enhance space and line pattern resolution independently on a given phase-shifting photomask (PSM). The disclosed techniques can be implemented, for example, to extend existing photolithography techniques/technologies (e.g., 193 nm photolithography) to additional process nodes. For instance, some embodiments can be used to produce extremely high-resolution photomasks which generate features having sizes in the 10 nm node and beyond. The disclosed techniques can be implemented in the fabrication of a wide range of integrated circuits (ICs) and other devices.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Inventor: Chang Ju Choi
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Patent number: 8399158Abstract: Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.Type: GrantFiled: December 23, 2010Date of Patent: March 19, 2013Assignee: Intel CorporationInventors: Chang Ju Choi, Cheng-Hsin Ma, Sven Henrichs, Robert H. Olshausen, Yulia Korobko
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Patent number: 8263769Abstract: Optically pure voriconazole can be prepared in a high yield by a) subjecting 1-(2,4-difluorophenyl)-2(1H-1,2,4-triazol-1-yl)ethanone to Reformatsky-type coupling reaction with a substituted thiopyrimidine derivative to obtain a desired (2R,3S)/(2S,3R)-enantiomeric pair; b) removing the thiol derivative from the enantiomer to obtain racemic voriconazole; and c) isolating the racemic voriconazole by way of optical resolution using an optically active acid.Type: GrantFiled: August 4, 2008Date of Patent: September 11, 2012Assignee: Hanmi ScienceInventors: Young Ho Moon, Moon Sub Lee, Jae Ho Yoo, Ji Sook Kim, Han Kyong Kim, Chang Ju Choi, Young Kil Chang, Gwan Sun Lee
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Publication number: 20120164563Abstract: Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Chang Ju Choi, Cheng-Hsin Ma, Sven Henrichs, Robert H. Olshausen, Yulia Korobko
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Patent number: 7799907Abstract: Provided is an improved method for stereoselectively preparing 2?-deoxy-2?,2?-difluorocytidine of formula (I), which includes reacting a 1-halo ribofuranose compound with a nucleobase of formula (IV) in a solvent to obtain a nucleo side of formula (II) with removal of a silyl halide ((alkyl)3SiX (X=halide)); and deprotecting the nucleoside of formula (II) to obtain 2?-deoxy-2?,2?-difluorocytidine of formula (I). 2?-Deoxy-2?,2?-difluorocytidine of formula (I) is effective for treating various cancers such as non-small cell lung (NSCLC), pancreatic, bladder, breast or ovarian cancers.Type: GrantFiled: December 29, 2005Date of Patent: September 21, 2010Assignee: Hanmi Pharm. Co., LtdInventors: Jaeheon Lee, Gha Seung Park, Moonsub Lee, Hyo-Jeong Bang, Jae Chul Lee, Cheol Kyong Kim, Chang-Ju Choi, Han Kyong Kim, Hoe Chul Lee, Young-Kil Chang, Gwan Sun Lee
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Publication number: 20100190983Abstract: Optically pure voriconazole can be prepared in a high yield by a) subjecting 1-(2,4-difluorophenyl)-2(1H-1,2,4-triazol-1-yl)ethanone to Reformatsky-type coupling reaction with a substituted thiopyrimidine derivative to obtain a desired (2R,3S)/(2S,3R)-enantiomeric pair; b) removing the thiol derivative from the enantiomer to obtain racemic voriconazole; and c) isolating the racemic voriconazole by way of optical resolution using an optically active acid.Type: ApplicationFiled: August 4, 2008Publication date: July 29, 2010Applicant: HANMI PHARM, CO., LTD.Inventors: Young Ho Moon, Moon Sub Lee, Jae Ho Yoo, Ji Sook Kim, Han Kyong Kim, Chang Ju Choi, Young Kil Chang, Gwan Sun Lee
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Publication number: 20090326234Abstract: Disclosed is (S)-(?)-amlodipine camsylate or a hydrate thereof having good photostability and high solubility, and a pharmaceutical composition comprising same, which can be efficiently used in treating cardiovascular diseases.Type: ApplicationFiled: July 16, 2007Publication date: December 31, 2009Applicant: Hanmi Pharm Co., Ltd.Inventors: Jaeheon Lee, Moon Sub Lee, Weon Ki Yang, Jaeho Yoo, Jae-Chul Lee, Chang-Ju Choi, Han Kyong Kim, Young-Kil Chang, Gwansun Lee
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Publication number: 20070249818Abstract: This invention relates to an improved method for stereoselectively preparing 2¢¥-deoxy-2¢¥,2¢¥-difluorocytidine of formula (I), which comprises the steps of reacting a 1-halo ribofuranose compound of formula (III) with a nucleobase of formula (IV) in a solvent to obtain a nucleoside of formula (II) with removing the silyl halide of formula (V) produced during the reaction; and deprotecting the nucleoside of formula (II) to obtain 2¢¥-deoxy-2¢¥,2¢¥-difluorocytidine of formula (I).Type: ApplicationFiled: December 29, 2003Publication date: October 25, 2007Applicant: Hanmi Pharm. Co.,LtdInventors: Jaeheon Lee, Gha Seung Park, Moonsub Lee, Hyo-Jeong Bang, Jae Lee, Cheol Kim, Chang-Ju Choi, Han Kyong Kim, Hoe Chul Lee, Young-Kil Chang, Gwan Lee
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Patent number: 7205164Abstract: Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.Type: GrantFiled: January 19, 2005Date of Patent: April 17, 2007Assignee: Silicon Magnetic SystemsInventors: Sam Geha, Benjamin C. E. Schwarz, Chang Ju Choi, Biju Parameshwaran, Eugene Y. Chen, Helen L. Chung, Kamel Ounadjela, Witold Kula
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Patent number: 6759339Abstract: A method is provided which includes pulsing power applied to a microelectronic topography between a high level and a low level during a plasma etch process. In particular, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the reaction chamber at the high level. In contrast, the low level may be sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. In this manner, an etched topography may be formed without an accumulation of residue upon its periphery. Such a method may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds, such as in the fabrication of a magnetic junction of an MRAM device, for example.Type: GrantFiled: December 13, 2002Date of Patent: July 6, 2004Assignee: Silicon Magnetic SystemsInventors: Chang Ju Choi, Benjamin Schwarz
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Patent number: 6391659Abstract: There is provided a method for fabricating a ferroelectric memory device, which can prevent the deterioration of the ferroelectric characteristics from etching damage generated during etching process of the interlayer-insulating layer formed over the capacitor to form a contact hole. The present invention is characterized by etching the interlayer-insulating layer with the use of time-modulated plasma, namely pulsed-power plasma. Accordingly, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.Type: GrantFiled: May 10, 2000Date of Patent: May 21, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: O-Sung Kwon, Chang-Ju Choi
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Publication number: 20020045279Abstract: There is provided a method for fabricating a ferroelectric memory device, which can prevent the deterioration of the ferroelectric characteristics from etching damage generated during etching process of the interlayer-insulating layer formed over the capacitor to form a contact hole. The present invention is characterized by etching the interlayer-insulating layer with the use of time-modulated plasma, namely pulsed-power plasma. Accordingly, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.Type: ApplicationFiled: May 10, 2000Publication date: April 18, 2002Inventors: O-Sung Kwon, Chang-Ju Choi
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Patent number: 5785797Abstract: A method of and an apparatus for monitoring etching by-products, capable of detecting and analyzing laser induced fluorescent light generated upon irradiating laser beams onto a by-product formed in the etching process. The method includes the steps of: selecting an excited electron level capable of being borne by molecules or radicals of the by-product; irradiating onto the by-product a laser beam with energy of a wavelength corresponding to the selected excited electron level; optionally exciting the molecules or radicals of the by-product by the irradiated laser beam, thereby forming a primary excited state of the by-product; detecting a laser induced fluorescent light emitted from the by-product during the transition of the by-product from the primary excited state to a secondary excited state which exhibits an energy level lower than the primary excited state; and analyzing the detected laser induced fluorescent light.Type: GrantFiled: October 21, 1997Date of Patent: July 28, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Chang Ju Choi