Abstract: Rendering images on an active area of an OLED includes rendering images on the active area of the display panel with a plurality of different frame rates. For a plurality of the different frame rates having a frame rate that matches or is above a threshold frame rate, an image refresh operation is performed once per frame period and a self-refresh operation is not performed during the frame period. When rendering images on the active area, for at least one of the different frame rates having a frame rate that is lower than the threshold frame rate, an image refresh operation is performed once per frame period and a self-refresh operation is performed at least once during the frame period.

Abstract: A display module is described that has two or more front-facing camera modules at opposing edges of a computing device. Using images acquired by both camera modules, when a user is looking directly at the display, it is possible to generate an image of the user as though he/she was looking directly toward the lens of a camera module.

Abstract: This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.

Abstract: This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.

Abstract: A flat panel display that includes a switch bank to couple a signal from a driver integrated circuit to a column data line of a display panel is disclosed. The switch bank can be adjusted based on the frame rate of the display. When the frame rate is high, all sub-switches in the switch bank may be used to reduce an ON resistance of the switch bank. This high frame rate configuration may maintain or increase the speed at which pixels can be controlled but consumes more power. Accordingly, when the frame rate is low, a portion of the sub-switches in the switch bank are unused to reduce the power consumed. This low frame rate configuration may maintain or decrease the speed at which pixels of the display can be controlled but consumes less power.

Abstract: A flat panel display that includes a switch bank to couple a signal from a driver integrated circuit to a column data line of a display panel is disclosed. The switch bank can be adjusted based on the frame rate of the display. When the frame rate is high, all sub-switches in the switch bank may be used to reduce an ON resistance of the switch bank. This high frame rate configuration may maintain or increase the speed at which pixels can be controlled but consumes more power. Accordingly, when the frame rate is low, a portion of the sub-switches in the switch bank are unused to reduce the power consumed. This low frame rate configuration may maintain or decrease the speed at which pixels of the display can be controlled but consumes less power.