Abstract: A semiconductor device includes: a substrate; a plurality of memory cells positioned over the substrate, each of the plurality of memory cells having a multi-layer structure including a memory pattern; a sealing layer pattern filling a lower portion of a space between the memory cells, the lower portion being positioned below a bottom surface of the memory pattern; a liner layer pattern formed along a surface of an upper portion of the space to partially fill the upper portion; and a dielectric layer pattern filling a remaining portion of the space unfilled by the sealing layer pattern and the liner layer pattern.

Abstract: A method for fabricating a semiconductor memory device includes defining an active region having a shape protruding upward by forming a trench in a semiconductor substrate; forming an open region obtained by selectively exposing a lower side portion of the active region while forming a sidewall layer along the shape of the active region; covering the open region with a silicon layer; forming an impurity region in the lower side portion of the active region; forming a barrier metal layer on the silicon layer and the active region; forming a bit line metal layer buried in the entire active region; and forming a buried bit line having the barrier metal layer, the bit line metal layer and a silicide metal layer formed between the silicon layer and the barrier metal layer by etching the bit line metal layer up to a portion at which the impurity region is formed.

Abstract: A method for fabricating a semiconductor memory device includes defining an active region having a shape protruding upward by forming a trench in a semiconductor substrate; forming an open region obtained by selectively exposing a lower side portion of the active region while forming a sidewall layer along the shape of the active region; covering the open region with a silicon layer; forming an impurity region in the lower side portion of the active region; forming a barrier metal layer on the silicon layer and the active region; forming a bit line metal layer buried in the entire active region; and forming a buried bit line having the barrier metal layer, the bit line metal layer and a silicide metal layer formed between the silicon layer and the barrier metal layer by etching the bit line metal layer up to a portion at which the impurity region is formed.

Abstract: A method for forming a metal line of a semiconductor device includes forming an insulation layer having a contact hole over a semiconductor substrate. Any one of a TiN layer and a TaN layer is formed on the insulation layer, including a surface of the contact hole, and an anti-reflection layer is formed on any one of the TiN layer and the TaN layer. A trench is defined at an upper end of the contact hole by etching the anti-reflection layer, any one of the TiN layer and the TaN layer, and the insulation layer. Subsequently, the anti-reflection layer is removed and a metal layer is formed to fill the trench and the contact hole.

Abstract: A dual damascene method of forming a metal line of a semiconductor device includes the procedures of: forming, partially annealing, etching, and cleaning. The forming procedure includes forming an SOD (spin-on dielectric) layer on an insulation layer having a contact hole to fill the contact hole. The partially annealing procedure includes annealing the SOD layer to selectively bake portions of the SOD layer which are filled in an upper portion of the contact hole and placed on the insulation layer. The etching procedure includes etching the baked portions of the SOD layer and a portion of the insulation layer to define a trench. The cleaning procedure includes cleaning the resultant structure of the trench and to remove substantially all of the unbaked portion of the SOD layer which remains in a lower portion of the contact hole.