Patents by Inventor Chang-Jung Hsueh
Chang-Jung Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230065797Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: August 26, 2021Publication date: March 2, 2023Inventors: Hui-Min HUANG, Ming-Da CHENG, Chang-Jung HSUEH, Wei-Hung LIN, Kai Jun ZHAN, Wan-Yu CHIANG
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Publication number: 20230063127Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
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Publication number: 20230065724Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Ming-Da Cheng, Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Po-Hao Tsai, Yung-Sheng Lin
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Publication number: 20230062370Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Patent number: 11569419Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.Type: GrantFiled: October 30, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
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Publication number: 20220278071Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.Type: ApplicationFiled: July 8, 2021Publication date: September 1, 2022Inventors: Kai Jun ZHAN, Chang-Jung HSUEH, Hui-Min HUANG, Wei-Hung LIN, Ming-Da CHENG
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Publication number: 20220140197Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
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Patent number: 11171100Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.Type: GrantFiled: November 27, 2019Date of Patent: November 9, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Hui-Min Huang, Wei-Hung Lin, Wen-Hsiung Lu, Ming-Da Cheng, Chang-Jung Hsueh, Kuan-Liang Lai
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Publication number: 20210265165Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
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Patent number: 11094655Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.Type: GrantFiled: June 13, 2019Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Hsiung Lu, Chang-Jung Hsueh, Chin-Wei Kang, Hui-Min Huang, Wei-Hung Lin, Cheng-Jen Lin, Ming-Da Cheng, Chien-Chun Wang
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Publication number: 20210159197Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Hui-Min HUANG, Wei-Hung LIN, Wen-Hsiung LU, Ming-Da CHENG, Chang-Jung HSUEH, Kuan-Liang LAI
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Patent number: 11004685Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.Type: GrantFiled: November 25, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
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Publication number: 20200395323Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.Type: ApplicationFiled: June 13, 2019Publication date: December 17, 2020Inventors: Wen-Hsiung LU, Chang-Jung HSUEH, Chin-Wei KANG, Hui-Min HUANG, Wei-Hung LIN, Cheng-Jen LIN, Ming-Da CHENG, Chien-Chun WANG
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Publication number: 20200176254Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.Type: ApplicationFiled: November 25, 2019Publication date: June 4, 2020Inventors: Chang-Jung Hsueh, Chen-En Yen, Kang Chin Wei, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii