Patents by Inventor Chang Kai-Cheng

Chang Kai-Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190155507
    Abstract: A method for performing system backup in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The memory device includes a non-volatile (NV) memory including at least one NV memory element. The method may include: writing system information of the memory device at a plurality of locations within the NV memory to make the system information be stored at a first location and a second location within the plurality of locations, respectively, wherein the system information is internal control information of the memory device, and the system information stored at the second location is equivalent to that stored at the first location; and when the system information stored at the first location is not available, reading the system information stored at the second location to control the memory device to operate according to the system information read from the second location.
    Type: Application
    Filed: April 9, 2018
    Publication date: May 23, 2019
    Inventors: Chang-Kai Cheng, Shen-Ting Chiu, Jing-Yi Chen
  • Patent number: 10120752
    Abstract: The present invention provides a data-storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector, and the spare data sector respectively corresponds to the sub-pages. The controller is arranged to access the sub-pages according to the spare data sector.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: November 6, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Li-Shuo Hsiao, Chang-Kai Cheng
  • Patent number: 10048870
    Abstract: In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 14, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Kai Cheng, Yu-Chih Lin
  • Patent number: 10007601
    Abstract: A data storage device and operating method for a FLASH memory are disclosed. The data storage device includes a FLASH memory and a controller. The FLASH memory includes a first block and a second block. The first and second blocks each includes a plurality of pages. The controller executes a firmware to determine whether a data segment from a host is a complete page segment. When the data segment is a complete page segment, the controller stores the data segment into the first block. When the data segment is an incomplete page segment, the controller stores the data into segment the second block.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: June 26, 2018
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Publication number: 20180107405
    Abstract: In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Inventors: Chang-Kai CHENG, Yu-Chih LIN
  • Patent number: 9875032
    Abstract: The present invention provides a data storage device including a flash memory, a controller and a delay circuit. The controller receives a read command from a host, reads a first data sector from the flash memory according to the read command, and produces a setting signal according to the maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit receives the setting signal from the controller, divides the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmits at least one of the first sub-data sectors to the host at a predetermined time interval for extending the busy time of the controller.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 23, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Kai Cheng, Yu-Chih Lin
  • Publication number: 20170364277
    Abstract: The present invention provides a data storage device including a flash memory, a controller and a delay circuit. The controller receives a read command from a host, reads a first data sector from the flash memory according to the read command, and produces a setting signal according to the maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit receives the setting signal from the controller, divides the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmits at least one of the first sub-data sectors to the host at a predetermined time interval for extending the busy time of the controller.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 21, 2017
    Inventors: Chang-Kai CHENG, Yu-Chih LIN
  • Publication number: 20170344423
    Abstract: The present invention provides a data-storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector, and the spare data sector respectively corresponds to the sub-pages. The controller is arranged to access the sub-pages according to the spare data sector.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventors: Li-Shuo HSIAO, Chang-Kai CHENG
  • Patent number: 9766974
    Abstract: The present invention provides a data-storage device including a flash memory and a controller. The flash memory includes a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector, and the spare data sector respectively corresponds to the sub-pages. The controller is arranged to access the sub-pages according to the spare data sector.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: September 19, 2017
    Assignee: SILICON MOTION, INC.
    Inventors: Li-Shuo Hsiao, Chang-Kai Cheng
  • Patent number: 9690695
    Abstract: A mapping table H2F update technique for a FLASH memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the FLASH memory in accordance with a group count of a buffer block of the FLASH memory. The group count reflects a logical address distribution of write data buffered in the buffer block and with non-updated logical-to-physical address mapping information. The higher the group count, the more dispersed the logical address distribution. In this manner, each update of the logical-to-physical address mapping table just takes a short time.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 27, 2017
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9600408
    Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current programming data block, determines whether a current programming page is a first page of the current programming data block, determines whether data move information is set when the current page is not the first page, and when the data move information is set, perform a data move process according to the data move information within a limited time period.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 21, 2017
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Kai Cheng, Yen-Hung Lin
  • Patent number: 9563551
    Abstract: A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: February 7, 2017
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9563550
    Abstract: A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 7, 2017
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9436599
    Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: September 6, 2016
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Kai Cheng, Kuan-Yu Ke
  • Patent number: 9355028
    Abstract: A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: May 31, 2016
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9304686
    Abstract: A data storage device is disclosed. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each block comprises a plurality of pages, and each page comprises a plurality of data trimming units which is a smallest unit for data modification. After a data trimming process has been performed on an address range of the flash memory, the controller determines a last page corresponding to an ending address of the address range, determines whether data values stored in the last page with addresses subsequent to the ending address are all equal to a specific data pattern, and sets the value of a trimming flag corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending address are all equal to the specific data pattern.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 5, 2016
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9244833
    Abstract: FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: January 26, 2016
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Publication number: 20160004468
    Abstract: A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided.
    Type: Application
    Filed: September 11, 2015
    Publication date: January 7, 2016
    Inventor: Chang-Kai CHENG
  • Patent number: 9223691
    Abstract: A data storage includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein the spare blocks with erase counts higher than a hot threshold are determined as hot spare blocks, and a hot spare block count indicates a total number of the hot spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the hot spare block count is greater than zero when the current programming page is the first page, and sets data move information for a wear-leveling process when the hot spare block count is greater than zero.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: December 29, 2015
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Kai Cheng, Yen-Hung Lin
  • Patent number: 9208074
    Abstract: A mapping table H2F update technique for a FLASH memory is disclosed. In the disclosed data storage device, when a master buffer block selected from a plurality of blocks of a FLASH memory to buffer write data from a host is full, the controller updates a logical-to-physical address mapping table for the master buffer block in separated update sub-intervals. Between the separated update sub-intervals, the controller responds to commands from the host. In this manner, commands from the host are responded to in a timely manner, without being postponed by a time-consuming mapping-table update of an entire buffer block.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 8, 2015
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng